Fault grading

Abstract: The principles of fault simulation and fault grading are introduced by a general description of the problem. Based upon the well-known concept of restricting fault simulation to the fanout stems and of combining it with a backward traversal inside the fanout-free regions of the circuit, proposals are presented to further accelerate fault simulation and fault grading. These proposals aim at parallel processing of patterns at all stages of the calculation procedure, at reducing the number of fanout stems for which a fault simulation has to be carried out, and at taking advantage of structural characteristics of the circuit. An experiment with a set of benchmark circuits demonstrates the efficiency of the proposed approaches.

Abstract: List of Figure. List of Tables. Preface. Contributors. 1. Introduction. Motivation. History. Current Research. Influence of Digital Test. Analog Test Issues. Test Paradigms. Organization. Conclusion. 2. Defect-Oriented Testing. Introduction. Previous Work. Estimation Method. Topological Method. Taxonomical Method. Defect-Based Realistic Fault Dictionary. Implementation. A Case Study. Fault Matrix Generation. Stimuli Matrix. Simulation Results. Silicon Results. Observations and Analysis. IFA-based Fault Grading and DFT for Analog Circuits. A/D Converter Testing. Description of the Experiment. Fault Simulation Issues. Fault Simulation Results. Analysis. DFT Measures. High-Level Analog Fault Models. Discussion: Strengths and Weaknesses of IFA-Based Tests. 3. Fault Simulation. Introduction. Why Analog Fault Simulation? Analog Fault Models and What-if Analysis. Focus and Organization. Fault Simulation of Linear Analog Circuits. Householder's Formula. Discrete Z-domain Mapping. Fault Bands and Band Faults. Interval-Mathematics Approach. Summary. C Fault Simulation of Nonlinear Analog Circuits. The Complementary Pivot Method. Fault Simulation via One-Step Relaxation. Simulation by Fault Ordering. Handling Statistical Variations. Summary. Fault Co-Simulation with Multiple Levels of Abstraction. Mixed-Signal Simulators. Incorporating Behavioral Models in Fault Simulation. Fault Macromodeling and Induced Behavioral Fault Modeling. Statistical Behavioral Modeling. Remarks on Hardware Description Languages. Concluding Remarks. 4. Automatic Test Generation Algorithms. Introduction. Fundamental Issues in Analog ATPG. Structural Test Versus Functional Test. Path Sensitization. Measurement Impact on Test Generation. Simulation Impact on Test Generation. Test Generation Algorithms and Results. Functional Test Generation Algorithms. Structural Test Generation Algorithms. ATPG Based on Automatic Test Selection Algorithms. DFT-based Analog ATPG Algorithms. Conclusions. 5. Design for Test. Preliminaries. Analog Characteristics. Common Characteristics. Generic Test Techniques. Increased Controllability/Observability. A/D Boundary Control. System-Specific Test Techniques. Analog Scan. Boundary Scan. Macro-Based DFT. Operational Amplifiers. Data Converters. Filters. Quality Analysis. Preliminaries. Analysis. Analysis. Conclusion. 6. Spectrum-Based Built-in Self-Test. Introduction. Some Early BIST Schemes. On-Chip Signal Generation. Digital Frequency Synthesis. Delta-Sigma Oscillators. Fixed-Length Periodic Bit Stream. Parameter Analysis. Fast Fourier Transform. Sinewave Correlation. Bandpass Filters. Application: MADBIST. Baseband MADBIST. Baseband MADBIST Experiments. MADBIST for Transceiver Circuits. Conclusions and Future Directions. 7. Implementing the 1149.4 Standard Mixed-Signal Test Bus. Overview of 1149.1 and 1149.4186. Test Functions Needed to Implement 1149.4189. Test Capabilities That This Standard Facilitates. Resistance, Capacitance, and Inductance Measurement. Measuring DC Parameters of Inputs and Outputs. Differential Measurements. Bandwidth. Delay Measurement. Potential Benefits of Using This Standard. Costs of Implementing This Standard on an IC. Practical Circuits Compliant with the Standard (Draft 18). Achieving Measurement Accuracy. DC Measurement Errors. AC Measurement Errors. Noise. Lessons from Test ICs. IMP (International Microelectronics Products) IC. Matsushita IC. Conclusions. 8. Test Techniques for CMOS Switched-Current Circuits. Introduction. Current Copiers: Basic Building Blocks of SI Circuits. Structure and Operation. Testing Current Copiers. Testing of Switched-Current Algorithmic A/D Converters. Structure and Operation. Concurrent Error Detection (CED). Test Generation. BIST Design. Scan Structures: Design for Testability. Conclusion. Index.

Abstract: The authors examine the question of whether fault grading is necessary and if yes, how high the single-stuck fault coverage must be? They show that, not only is fault grading required, but that extremely high single stuck fault coverage is probable necessary. The results presented are extensions of previous work in this area by T.W. Williams (1985). The authors discuss only functional or Boolean testing, which does not involve measurement, but determines whether logic functions are correct. The question of how thorough a Boolean test procedure need be is the main focus. The need for extremely thorough testing is demonstrated. >

Abstract: Inductive Fault Analysis (IFA) for analog circuits has received considerable attention in recent years. IFA can be exploited for simplifying various aspects of analog testing. It can also be exploited towards design robustness against process defects, fault grading of a design and examining practicality of analog DfT schemes. In this article, we analyse both aspects of analog IFA with real life examples. Towards the test side, the simulated as well as silicon data demonstrate the strengths of IFA based test methods in test cost reduction and structural test generation. However, some of the escaped devices suggest partial specification testing along with IFA based test is desirable from a quality as well as economic point of view. Towards the design side, the simulation results highlight macros where DfT is needed most and help in determination of effective DfT schemes.