Topic
Fast interrupt request
About: Fast interrupt request is a research topic. Over the lifetime, 7 publications have been published within this topic receiving 67 citations.
Papers
Patent•
31 Jul 1978TL;DR: In this paper, a method of performing a fast interrupt in a digital data processor having the capability of handling more than one interrupt is provided, where a flag is set and the program counter and condition code registers are stored on a stack.
Abstract: A method of performing a fast interrupt in a digital data processor having the capability of handling more than one interrupt is provided. When a fast interrupt request is received a flag is set and the program counter and condition code registers are stored on a stack. At the end of the interrupt servicing routine the return from interrupt instructions retrieves the condition code register which contains the status of the digital data processor and checks to see whether the flag has been set or not. If the flag is set it indicates that a fast interrupt was serviced and therefore only the program counter is unstacked.
48 citations
Patent•
21 Oct 2015
TL;DR: In this paper, a cell phone private information safe box based on an ARM trust zone is presented. But the security of the cell phone's private information is not discussed. But it is assumed that the user of a security zone can selectively carry out a security operating procedure or store a cell-phone private document, and utilizes an encryption function provided by the ARM Trust Zone to carry out encryption and decryption.
Abstract: The invention discloses a cell phone private information safe box based on an ARM Trust Zone. The cell phone private information safe box comprises a common zone operating system (Rish OS) and a security zone operating system (Security OS); when the common region zone operating system is switched to the security zone operating system, a monitor mode provided by the ARM Trust Zone is needed; a user sends a fast interrupt request (FIQ) through the common zone operating system to enter the monitor mode; under the monitor mode, an NS site of a security configuration register (SCR) of an ARM processor is modified and is set to be 0, so that a CPU status is switched to the security zone operating system; and a user of a security zone can selectively carry out a security operating procedure or store a cell phone private document, and utilizes an encryption function provided by the CPU of the ARM Trust Zone to carry out encryption and decryption on the security zone. According to the cell phone private information safe box provided by the invention, the cell phone private document and software with high-security requirements are preserved in the security region by a user of a common zone through simple operation, and the private document of the user in the security zone is encrypted and decrypted; and meanwhile, the user can safely operate application programs with high-security requirements.
7 citations
1 Jan 2020
TL;DR: This article presents the use of ARM's fast interrupt request (FIQ) to accomplish better jitter performance on real‐time drivers without using patches for real-time extensions on the native Linux kernel code.
7 citations
Patent•
11 Oct 2012TL;DR: In this article, the authors describe a low-latency low-interference system for operating system aware low latency handling using a non-transitory computer readable storage medium including a set of instructions executable by a processor, when executed, resulting in a performance of receiving a fast interrupt request asserted by a hardware device.
Abstract: The exemplary embodiments described herein relate to systems and methods for operating system aware low latency handling. One embodiment relates to a non-transitory computer readable storage medium including a set of instructions executable by a processor, the set of instructions, when executed, resulting in a performance of receiving a fast interrupt request asserted by a hardware device while the processor is executing within a kernel critical section, executing a fast interrupt handler at a first priority level, raising a second priority level interrupt by the fast interrupt handler based on the fast interrupt request, wherein the second priority level interrupt invokes a kernel service and processing the second priority level interrupt once the processor has executed the kernel critical section.
2 citations
Performance Metrics
| Year | Papers |
|---|---|
| 2020 | 2 |
| 2015 | 1 |
| 2012 | 1 |
| 2011 | 1 |
| 2004 | 1 |
| 1978 | 1 |