Topic
External Bus Interface
About: External Bus Interface is a research topic. Over the lifetime, 1457 publications have been published within this topic receiving 20196 citations.
Papers published on a yearly basis
Papers
Patent•
4 Apr 1997TL;DR: In this paper, an integrated circuit (2210) for use with a first processor (106) off-chip, the following combination: first terminals (of 2232) for first processor related signals and defining a first data width (32-bit), second terminals for external bus-related signals (PCI), third terminals for memory related signals (of 2258), and a DRAM memory controller (2250) connected to the third terminals.
Abstract: An integrated circuit (2210) provides on a single chip for use with a first processor (106) off-chip, the following combination: first terminals (of 2232) for first processor-related signals and defining a first data width (32-bit), second terminals for external bus-related signals (PCI), third terminals for memory-related signals (of 2258), and a DRAM memory controller (2250) connected to the third terminals. Further on chip is provided an arbiter circuit (2230), a bus bridge circuit (2236) coupled to the DRAM memory controller and to the second terminals, the bus bridge (2236) also coupled to the arbiter (2230), a second processor (2224) having a second data width (16-bit), and a bus interface circuit (2220) coupling the second data width of the second processor (2224) to the first data width. The bus interface circuit (2220) further has bus master and bus slave circuitry coupled between the second processor (2224) and the arbiter circuit (2230). The bus bridge (2236), the bus interface (2220) and the first terminals and the DRAM memory controller (2250) have datapaths selectively interconnected in response to the arbiter circuit (2230). Other devices, systems and methods are also disclosed.
297 citations
1 May 1996
TL;DR: The motivation for building STiNG as well as its architecture and implementation are described, and performance analysis is provided for On-Line Transaction Processing (OLTP) and Decision Support System (DSS) workloads.
Abstract: "STiNG" is a Cache Coherent Non-Uniform Memory Access (CC-NUMA) Multiprocessor designed and built by Sequent Computer Systems, Inc. It combines four processor Symmetric Multi-processor (SMP) nodes (called Quads), using a Scalable Coherent Interface (SCI) based coherent interconnect. The Quads are based on the Intel P6 processor and the external bus it defines. In addition to 4 P6 processors, each Quad may contain up to 4 GBytes of system memory, 2 Peripheral Component Interface (PCI) busses for I/O, and a Lynx board. The Lynx board provides the datapath to the SCI-based interconnect and ensures system-wide cache coherency. STiNG is one of the first commercial CC-NUMA systems to be built. This paper describes the motivation for building STiNG as well as its architecture and implementation. In addition, performance analysis is provided for On-Line Transaction Processing (OLTP) and Decision Support System (DSS) workloads. Finally, the status of the current implementation is reviewed.
271 citations
Patent•
30 Aug 1995TL;DR: In this article, a debug module of a data processor (3) provides a parallel output port for providing internal operating information via a DDATA signal and a PST signal, which allows an external development system (7) to dynamically observe internal operations of data processor without assuming a type or availability of an external bus and without significantly impacting the efficiency and speed of the data processor.
Abstract: A data processor (3) executes a real time trace function which allows an external development system (7) to dynamically observe internal operations of data processor (3) without assuming a type or availability of an external bus and without significantly impacting the efficiency and speed of the data processor (3). A debug module (10) of data processor (3) provides a parallel output port for providing internal operating information via a DDATA signal and a PST signal. The DDATA signal provides data which reflects operand values and the PST signal provides encoded status information which reflects an execution status of a central processing unit 92). Furthermore, the DDATA signal also provides captured instruction address program flow changes to allow external development system (7) to trace an exact program flow without requiring an externally visible address bus or an externally visible data bus.
207 citations
Patent•
2 Mar 1994TL;DR: In this article, an external bus request queue is used to monitor and control the issuance of data requests, such as read requests and write requests, onto the external bus in a multi-level hierarchical memory system.
Abstract: A computer system, and a method performed by it, having a mechanism for ensuring consistency of data among various level(s) of caching in a multi-level hierarchical memory system. The cache consistency mechanism includes an external bus request queue which and associated mechanism, which cooperate to monitor and control the issuance of data requests, such as read requests and write requests, onto an external bus. The computer system includes one or more CPUs each having this consistency mechanism.
203 citations
Patent•
10 Aug 1994
TL;DR: In an evaluation single-chip microcomputer which includes circuit elements connected to an internal bus and capable of storing data or of arithmetic operation, the contents of the circuit elements being required to be known outside of the microcomputer, a control circuit decodes instructions supplied through theInternal bus and produces control signals for controlling the operations of the Circuit elements.
Abstract: A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.
203 citations
Related Topics (5)
Performance Metrics
| Year | Papers |
|---|---|
| 2021 | 2 |
| 2020 | 6 |
| 2019 | 8 |
| 2018 | 16 |
| 2017 | 20 |
| 2016 | 17 |