Exabit

Abstract: Methods for performing packet classification via prefix pair bit vectors. Unique prefix pairs in an access control list (ACL) are identified, with each prefix pair comprising a unique combination of a source prefix and a destination prefix. Corresponding prefix pair bit vectors (PPBVs) are defined for each unique source prefix and unique destination prefix in the ACL, with each PPBV including a string of bits and each bit position in the string associated with a corresponding prefix pair. A list of transport field value combinations are associated with each prefix pair based on corresponding entries in the ACL. During packet-processing operations, PPBV lookups are made using the source and destination prefix header values, and the PPBVs are logically ANDed to identify applicable prefix pairs. A search is then performed on transport field value combinations corresponding to the prefix pairs and the packet header to identify a highest priority rule.

Abstract: This specification describes a system for preventing the catastrophic loss of data in one storage unit of a storage system comprised of a plurality of such storage units. In this system one of the plurality of storage units is used to store parity bits for the storage system, bit position by bit position. To be more specific, if the data in each of the storage units is considered to be a linear string of bits the storage unit containing the parity bits would contain a parity or Exclusive OR sum of all the first bits of all the storage units or, in a more general case, the j.sup.th bit of the check storage unit is the parity or Exclusive OR sum of all the j bits of all the storage units.

Abstract: A prefix decoder for decoding a plurality of prefixes of a variable length instruction code, in order to supply multiple prefix vectors to a multiple instruction decoder without incurring a one clock penalty. The parallel prefix decoder includes a plurality of prefix decoders, each coupled to receive an instruction byte from an instruction buffer, and in response thereto to supply a prefix vector that includes coded prefix information in a format that is easy to use by subsequent decoder logic. A multiplexer receives the plurality of prefix vectors, and if a steered macroinstruction has a single prefix byte, then a control circuit selects the prefix vector to supply to the macroinstruction decoder. If multiple macroinstructions are steered to multiple macroinstruction decoders, then a prefix vector can be supplied to each decoder.