TL;DR: A set of command injection, data injection, and denial of service attacks which leverage the lack of authentication in many common control system communication protocols including MODBUS, DNP3, and EtherNET/IP are developed.
Abstract: SCADA systems are widely used in critical infrastructure sectors, including electricity generation and distribution, oil and gas production and distribution, and water treatment and distribution. SCADA process control systems are typically isolated from the internet via firewalls. However, they may still be subject to illicit cyber penetrations and may be subject to cyber threats from disgruntled insiders. We have developed a set of command injection, data injection, and denial of service attacks which leverage the lack of authentication in many common control system communication protocols including MODBUS, DNP3, and EtherNET/IP. We used these exploits to aid in development of a neural network based intrusion detection system which monitors control system physical behavior to detect artifacts of command and response injection attacks. Finally, we present intrusion detection accuracy results for our neural network based IDS which includes input features derived from physical properties of the control system.
TL;DR: The goal of MiniCPS is to create an extensible, reproducible research environment for network communications, control systems, and physical-layer interactions in CPS, and to establish a framework to connect together real CPS soft- and hardware, simulation scripts for such components, andPhysical-layer simulation engines.
Abstract: In recent years, tremendous effort has been spent to modernizing communication infrastructure in Cyber-Physical Systems (CPS) such as Industrial Control Systems (ICS) and related Supervisory Control and Data Acquisition (SCADA) systems. While a great amount of research has been conducted on network security of office and home networks, recently the security of CPS and related systems has gained increased attention. Unfortunately, real-world CPS are often not open to security researchers, and as a result very few reference physical-layer processes, control systems and communication topologies are available.In this work, we present MiniCPS, a toolkit intended to alleviate this problem. The goal of MiniCPS is to create an extensible, reproducible research environment for network communications, control systems, and physical-layer interactions in CPS. Instead of focusing on a customized simulation settings for specific subsystems, the main goal is to establish a framework to connect together real CPS soft- and hardware, simulation scripts for such components, and physical-layer simulation engines. MiniCPS builds on Mininet to provide lightweight real-time network emulation, and extends Mininet with tools to simulate typical CPS components such as programmable logic controllers, which use industrial protocols (eg. EtherNet/IP, Modbus/TCP). To capture physical-layer interactions, MiniCPS defines a simple API to connect to physical-layer simulations. We demonstrate applications of MiniCPS in two example scenarios, and show how MiniCPS can be used to develop attacks and defenses that are directly applicable to real systems.
TL;DR: The basics of CIP are described and an overview over the newest member of this family of protocols - Ethernet/IP is given.
Abstract: DeviceNet and ControlNet are two well known members of the same family of protocols - the CIP family (CIP=Control an Information Protocol). Both protocols have been developed by Rockwell Automation, but are now owned and maintained by the two manufacturers organizations ODVA (Open DeviceNet Vendors Association, see http://www.odva.org) and ControlNet International (see http://www.controlnet.org/). ODVA and ControlNet International have recently introduced the newest member of this family - Ethernet/IP ("IP" stands for "Industrial Protocol"). This paper describes the basics of CIP and gives an overview over the newest member of this family of protocols - Ethernet/IP.
TL;DR: In this paper, a system and method for distributing satellite TV program signals utilizes IP and Ethernet multicast addresses to define and allow the acquisition and/or distribution of a particular satellite television program signal.
Abstract: A system and method for distributing satellite television program signals utilizes IP and Ethernet multicast addresses to define and allow the acquisition and/or distribution of a particular satellite television program signal. The satellite program identification data or parameters for the particular satellite program signal are encoded by an IP multicast address assigned to the particular satellite television program signal from a block of IP multicast addresses, preferably by a mini head end (40). The assigned IP multicast address is mapped to an Ethernet IP address for distribution to an Ethernet compatible component such as a satellite signal receiver or set top box. In this manner, any and all satellite program signals may be provided to one or more satellite signal receivers (32) through IP multicasting.
TL;DR: The subject paper proposes an approach to developing a design verification environment targeted towards complex application-specific integrated circuits (ASICs), with particular emphasis on embedded systems incorporating intellectual property (IP) cores.
Abstract: The subject paper proposes an approach to developing a design verification environment targeted towards complex application-specific integrated circuits (ASICs), with particular emphasis on embedded systems incorporating intellectual property (IP) cores. An emergent trend seems to realize this through the use of coverage-driven functional verification (CDV) and reuse methodology (RM). The CDV relies on the ASIC functionalities and the verification process is formalized in the early stages of the design cycle. The deterministic testing together with the CDV and RM is applied in the paper to specifically verify the design of Ethernet IP MAC cores from open cores The Specman Elite e-language originally developed by Cadence is utilized in the process as the verification tool on representative IP core design implementations.