TL;DR: High aspect ratio (HAR) silicon etch is reviewed in this paper, including commonly used terms, history, main applications, different technological methods, critical challenges, and main theories of the technologies.
Abstract: High aspect ratio (HAR) silicon etch is reviewed, including commonly used terms, history, main applications, different technological methods, critical challenges, and main theories of the technologies. Chronologically, HAR silicon etch has been conducted using wet etch in solution, reactive ion etch (RIE) in low density plasma, single-step etch at cryogenic conditions in inductively coupled plasma (ICP) combined with RIE, time-multiplexed deep silicon etch in ICP-RIE configuration reactor, and single-step etch in high density plasma at room or near room temperature. Key specifications are HAR, high etch rate, good trench sidewall profile with smooth surface, low aspect ratio dependent etch, and low etch loading effects. Till now, time-multiplexed etch process is a popular industrial practice but the intrinsic scalloped profile of a time-multiplexed etch process, resulting from alternating between passivation and etch, poses a challenge. Previously, HAR silicon etch was an application associated primarily with microelectromechanical systems. In recent years, through-silicon-via (TSV) etch applications for three-dimensional integrated circuit stacking technology has spurred research and development of this enabling technology. This potential large scale application requires HAR etch with high and stable throughput, controllable profile and surface properties, and low costs.
TL;DR: In this article, the etching behavior of highly boron doped silicon in aqueous solutions based of ethylenediamine, KOH, NaOH, and LiOH was studied.
Abstract: The etching behavior of highly boron doped silicon in aqueous solutions based of ethylenediamine, KOH, NaOH, and LiOH was studied. For all etchants, a strong reduction of the etch rate for boron concentrations exceeding approximately 2 �9 10 ~9 cm -3 was observed. This value is in good agreement with published data for the onset of degeneracy of p-type silicon. The reduction of the etch rate was found to be inversely proportional to the fourth power of the boron concentration. For a given high boron concentration, the etch stop effect was found to be most effective for ethylenediamine-based solutions and low concentration KOH and least effective for highly concentrated KOH. On the basis of these results, a model is proposed attributing the etch stop phenomenon to electrical effects of holes rather than chemical effects of boron. Due to the high dopant concentration the width of the space charge layer on the silicon surface shrinks drastically. Therefore, electrons injected into the conduction band by an oxidation reaction cannot be confined to the surface and rapidly recombine with holes from the valence band. The lack of these electrons impedes the reduction of water and thereby the formation of new hydroxide ions at the silicon surface. Since the transfer of four electrons is required for the dissolution of one silicon atom the observed fourth power law for the decrease of the etch rate can be explained. The reduction of the etch rate on silicon doped with germanium or phosphorus is much smaller and follows a different mechanism.
TL;DR: In this article, the authors fabricated gallium oxide (Ga2O3) Schottky barrier diodes using single-crystal substrates produced by the floating-zone method.
Abstract: We fabricated gallium oxide (Ga2O3) Schottky barrier diodes using β-Ga2O3 single-crystal substrates produced by the floating-zone method. The crystal quality of the substrates was excellent; the X-ray diffraction rocking curve peak had a full width at half-maximum of 32 arcsec, and the etch pit density was less than 1×104 cm-2. The devices exhibited good characteristics, such as an ideality factor close to unity and a reasonably high reverse breakdown voltage of about 150 V. The Schottky barrier height of the Pt/β-Ga2O3 interface was estimated to be 1.3-1.5 eV.
TL;DR: In this article, a resist layer is formed on an oxide layer on a substrate, and a photosensitive layer is created on the resist layer and patterned to expose regions of the oxide layer to be removed.
Abstract: A method of etching an oxide layer is disclosed. First, a resist layer is formed on an oxide layer on a substrate. Next, a photosensitive layer is formed on the oxide layer and patterned to expose regions of the oxide layer to be removed. The exposed regions may overlie a nitride layer, and may overlie a structure such as a polysilicon gate. The etch is performed such that polymer deposits on the photosensitive layer, thus eliminating interactions between the photosensitive layer and the plasma. In this way, a simple etch process allows for good control of the etch, resulting in reduced aspect ratio dependent etch effects, high oxide:nitride selectivity, and good wall angle profile control.
TL;DR: In this article, the orientation dependence in chemical anisotropic etching of single-crystal silicon was evaluated for a wide range of etching conditions, including KOH concentrations of 30 to 50% and temperatures of 40 to 90 °C.
Abstract: We have evaluated the orientation dependence in chemical anisotropic etching of single-crystal silicon. Etch rates for a number of crystallographic orientations have been measured for a wide range of etching conditions, including KOH concentrations of 30 to 50% and temperatures of 40 to 90 °C. Though the etchants all consist of the same components KOH and water, the orientation dependence varies considerably with change in etchant temperature and concentration. The resulting etch-rate database allows numerical prediction of etch profiles of silicon, necessary for the process design of microstructures. Changing the KOH concentration yields different etch profiles both analytically and experimentally.