Topic
ESD simulator
About: ESD simulator is a research topic. Over the lifetime, 35 publications have been published within this topic receiving 216 citations.
Papers
TL;DR: In this article, a travelling-wave electrostatic discharge (ESD) simulator with bench-top-scale dimensions is presented. But the design process utilized frequency-domain measurements and computer simulations of wave attenuation on the part of the simulator representing the human arm.
Abstract: Existing travelling-wave electrostatic discharge (ESD) simulators satisfactorily reproduce the characteristics of a human discharge but have dimensions comparable to a human subject, so they are inconveniently large for practical ESD susceptibility testing of electronic equipment. This paper describes the design of a compact travelling-wave ESD simulator with benchtop-scale dimensions. The design process utilized frequency-domain measurements and computer simulations of wave attenuation on the part of the simulator representing the human arm. From these results, it was deduced that the ESD simulator arm could be shortened from its original human-scale length of 60 cm to a more compact 30 cm without significantly affecting the currents flowing on it. The part of the simulator representing the human body was designed on the basis of capacitance. The resulting travelling-wave simulator (arm and body) is approximately half the size of the original simulator. Measurements are presented comparing the compact simulator with a previously-designed full-size simulator and with a human test subject, with regard to arm currents, swept-frequency input impedance, and capacitance.
36 citations
27 Mar 1990
TL;DR: In this paper, a three-dimensional thermal model to determine the temperature rise and voltage build-up of VLSI devices stressed by human-body model (HBM) electrostatic discharges (ESD) is discussed.
Abstract: A three-dimensional thermal model to determine the temperature rise and voltage build-up of VLSI devices stressed by human-body model (HBM) electrostatic discharges (ESD) is discussed. Application of the model to a specific device is yields failure thresholds and failure sites in agreement with the experimental results. This detailed model can be used to evaluate and improve designs of ESD protection circuits. It not only reconfirms the good design principles for ESD protection circuits, but also points out the importance of pulse risetime in determining the failure site. Allowing a wide range in risetime in ESD simulator specifications (such as the 0-10 ns range in MIL-STD Method 3015.6 Notice 7 and the 2-10 ns range in the EOS/ESD Association HBM Standard), may cause ESD pulses of different risetimes within the allowable range to deposit energy to different spots in a device and yield uncorrelatable ESD thresholds. >
23 citations
1 Sep 2004
TL;DR: An unexpected and serious effect from the ESD HBM tester causing gate oxide failure in input buffers is reported and safe control limits for proper output of the state-of-the-art ESD simulator waveforms are established.
Abstract: An unexpected and serious effect from the ESD HBM tester causing gate oxide failure in input buffers is reported in this paper. The most significant finding is that this unwarranted stress comes from the tester relay and gives rise to false HBM evaluation. In this paper we investigate this new effect on gate oxide reliability and establish the safe control limits for proper output of the state-of-the-art ESD simulator waveforms.
22 citations
TL;DR: An efficient, simple and fast equivalent circuit and full wave numerical modeling of the electrostatic discharge (ESD) generator is presented and good agreement between the ESD reference waveform obtained through measurement, circuit model and 3D model of the generator is observed.
Abstract: In this work, a new technique for an efficient, simple, and fast equivalent circuit and full wave numerical modeling of the electrostatic discharge (ESD) generator is presented. A novel circuit model of the NoiseKen ESD simulator is proposed based on the frequency domain measurement of the standard waveform calibration setup. The simple full wave electromagnetic model of the same generator, which requires much less computation resources, is also proposed using commercial CST Microwave Studio software. The reliability of the proposed models as an authentic ESD excitation source is validated through an example discharge application. The good agreement between the ESD reference waveform obtained through measurement, circuit model, and 3-D model of the generator is observed.
20 citations
21 Aug 1990
TL;DR: In this paper, the repeatability of electrostatic discharge (ESD) testing using commercially available, lumped capacitance ESD simulators is examined, and the pulse generated by the simulator and the indirect application of discharges using a flat, metallic coupling plane are studied.
Abstract: The repeatability of electrostatic discharge (ESD) testing using commercially available, lumped capacitance ESD simulators is examined. The pulse generated by the simulator and the indirect application of discharges using a flat, metallic coupling plane are studied. Some of the parameters that may affect repeatability are the angle between the simulator and the test sample or coupling plane, location of the discharge on the coupling plane, and the location of the simulator's ground return cable. It is concluded that using a lumped element ESD simulator and a flat metal plate is a viable method of testing an electronic product to determine its immunity to indirect ESD. >
18 citations
Related Topics (5)
Performance Metrics
| Year | Papers |
|---|---|
| 2018 | 4 |
| 2017 | 3 |
| 2015 | 1 |
| 2012 | 3 |
| 2010 | 1 |
| 2008 | 2 |