Topic
EPROM
About: EPROM is a research topic. Over the lifetime, 3161 publications have been published within this topic receiving 51983 citations. The topic is also known as: EPROM & erasable programmable ROM.
Papers published on a yearly basis
Papers
Patent•
2 Aug 1998
TL;DR: In this paper, an electrically erasable programmable read-only memory (EEPROM) with a non-conducting charge trapping dielectric, such as silicon nitride, sandwiched between two silicon dioxide layers acting as electrical insulators is disclosed.
Abstract: An electrically erasable programmable read only memory (EEPROM) having a non conducting charge trapping dielectric, such as silicon nitride, sandwiched between two silicon dioxide layers acting as electrical insulators is disclosed. The invention includes a method of programming, reading and erasing the EEPROM device. The non conducting dielectric layer functions as an electrical charge trapping medium. A conducting gate layer is placed over the upper silicon dioxide layer. The memory device is programmed in the conventional manner, using hot electron programming, by applying programming voltages to the gate and the drain while the source is grounded. Hot electrons are accelerated sufficiently to be injected into the region of the trapping dielectric layer near the drain. The device, however, is read in the opposite direction from which it was written, meaning voltages are applied to the gate and the source while the drain is grounded. Application of relatively low gate voltages combined with reading in the reverse direction greatly reduces the potential across the trapped charge region. This permits much shorter programming times by amplifying the effect of the charge trapped in the localized trapping region. In addition, the memory cell can be erased by applying suitable erase voltages to the gate and the drain so as to cause electrons to be removed from the charge trapping region of the nitride layer. Similar to programming, a narrower charge trapping region enables much faster erase cycles.
1,195 citations
Patent•
15 Oct 1991
TL;DR: In this article, an intelligent erase algorithm is used to prolong the useful life of the memory cells, which is useful as a solid state memory in place of magnetic disk storage devices in computer systems.
Abstract: Structures, methods of manufacturing and methods of use of electrically programmable read only memories (EPROM) and flash electrically erasable and programmable read only memories (EEPROM) include split channel and other cell configurations. An arrangement of elements and cooperative processes of manufacture provide self-alignment of the elements. An intelligent programming technique allows each memory cell to store more than the usual one bit of information. An intelligent erase algorithm prolongs the useful life of the memory cells. Use of these various features provides a memory having a very high storage density and a long life, making it particularly useful as a solid state memory in place of magnetic disk storage devices in computer systems.
1,037 citations
Patent•
24 Jun 1997
TL;DR: In this article, the authors proposed a method for programming and reading a programmable read only memory (EPROM) having a trapping dielectric layer (20) sandwiched between two silicon dioxide layers (18, 20) that greatly reduced the programming time of conventional PROM devices.
Abstract: A novel apparatus and method for programming and reading a programmable read only memory (EPROM) having a trapping dielectric layer (20) sandwiched between two silicon dioxide layers (18, 20) is disclosed that greatly reduces the programming time of conventional PROM devices. Examples of the trapping dielectric material are silicon oxide-silicon, nitride-silicon oxide (ONO) and silicon dioxide with buried polysilicon islands. A nonconducting dielectric layer functions as an electrical charge trapping medium. This charging trapping layer is sandwiched between two layers of silicon dioxide acting as an electrical insulator. A conducting gate layer (24) is placed over the upper silicon dioxide layer (22). The memory device (10) is programmed in the conventional manner. The device, however, is read in the opposite direction from which it was written, meaning voltages are applied to the gate (24) and the source (14) while the drain is grounded. For the same applied gate voltage, reading in the reverse direction greatly reduces the potential across the trapped charge region.
855 citations
15 Feb 1995
TL;DR: A 3.3 V-only 32 Mb NAND flash memory that achieves not only high performance but also low cost with a 94.9 mm/sup 2/ die size, improved yields, and a simple process with 0.5 /spl mu/m CMOS technology is described.
Abstract: While the performance of flash memory exceeds hard disk drives in almost every category, the cost of flash memory must come down in order to gain wider acceptance in mass storage applications. This paper describes a 3.3 V-only 32 Mb NAND flash memory that achieves not only high performance but also low cost with a 94.9 mm/sup 2/ die size, improved yields, and a simple process with 0.5 /spl mu/m CMOS technology. Die size is reduced by eliminating high voltage operation on the bitlines through a self boosted program inhibit voltage generation scheme. Incremental-step-pulse programming results in a 2.3 MB/s program data rate as well as improved process variation tolerance. Interleaved data paths and a boosted wordline results in a 25 ns burst cycle time and a 24 MB/s read data rate. Maximum operating current is less than 8 mA.
772 citations
Patent•
25 Jun 1993
TL;DR: In this article, column segmentation is used to isolate defects to individual segments and reduce the capacitance in the source and drain of an address memory cell, which enables the use of larger size segment-select transistors which are necessary for passing higher currents in devices such as EPROM or flash EEPROM.
Abstract: In an array of solid-state memory cells organized into rows and segmented columns and addressable by wordlines and bit lines, a memory cell within a segmented column is addressable by segment-select transistors which selectively connect the memory cell's pair of bit lines via conductive lines running parallel to the columns to a column decode circuit. The disposition of the segment-select transistors and the conductive lines relative to the segmented columns enables one segment-select transistor to fit in every two or more columns. In one embodiment, the segment-select transistors have double the pitch of the columns while the conductive lines have the same pitch of the columns. In another embodiment, the segment-select transistor have four times the pitch of the columns while the conductive lines have double the pitch of the columns. This enables the use of larger size segment-select transistors which are necessary for passing higher currents in devices such as EPROM or flash EEPROM. Column segmentation effectively isolates defects to individual segments and reduces the capacitance in the source and drain of an address memory cell.
575 citations
Related Topics (5)
Performance Metrics
| Year | Papers |
|---|---|
| 2023 | 10 |
| 2022 | 8 |
| 2021 | 7 |
| 2020 | 7 |
| 2019 | 10 |
| 2018 | 16 |