Abstract: Integrated semiconductor-on-insulator (SOI) sensors and circuits which are electrostatically bonded to a support substrate, such as glass or an oxidized silicon wafer, are disclosed. The SOI sensors and SOI circuits are both formed using a novel fabrication process which allows multiple preformed and pretested integrated circuits on a silicon wafer to be electrostatically bonded to the support substrate without exposing the sensitive active regions of the electronic devices therein to a damaging electric field. The process includes forming a composite bonding structure on top of the integrated circuits prior to the bonding step. This composite structure includes a conductive layer dielectrically isolated from the circuit devices and electrically connected to the silicon wafer, which is spaced form but laterally overlaps at least the active semiconductive regions of the circuit devices. The SOI sensors each include a transducer and at least one active electronic device, which are both made at least in part from a common layer of lightly-doped single-crystal semiconductor material grown on the silicon wafer. After the bonding step, the bulk of the single-crystal wafer is removed, leaving the epitaxial layer containing the circuits and transducers. The epitaxial layer is then patterned into isolated mesas to dielectrically isolate the electronic devices. This patterning step also exposes bond pads, allowing external connections to be readily made to the sensors and circuits. Exemplary solid-state sensors disclosed herein include a capacitive accelerometer and pressure sensor.

Abstract: The present invention is directed to a ceramic coated metal substrate having improved processibility characteristics in the manufacture of electronic devices, as for example electronic circuits, and to processes for manufacture of such devices.

Abstract: The authors performed a study to determine whether silicon very large-scale integrated circuits (VLSICs) can survive the high temperature (up to 300 degrees C) and total-dose radiation environments (up to 10 Mrad over a 7-10-y system life) projected for a very-high power space nuclear reactor platform. It is shown that circuits built on bulk epitaxial silicon cannot meet the temperature requirement because of excessive junction leakage currents. However, circuits built on silicon-on-insulator (SOI) material can meet both the radiation and temperature requirements. It is also found that the temperature dependence of the threshold voltage of the SOI transistors is less than that of bulk transistors. Survivability of high-temperature SOI VLSICs in space, including immunity to transient and single-event upset, is also addressed. >

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Abstract: This invention is a family of simple, inexpensive, and portable electronic devices for business support built around a simple 2-dimensional digitizing device. It includes a transmit-only facsimile transmission device/system, a simple computer-based facsimile system, and a dual-mode (digital or OCR) page reading device. The digitizing device includes a read bar having a linear read head for developing a signal reflecting a one dimensional line of viewing; apparatus for creating relative movement between sheets of material to be digitized and the read bar; and, a detector for developing a signal indicating movement of the sheets one scanned line distance. The simple transmit-only facsimile transmission system comprises the foregoing digitizing device and, a digital computer including a numeric input keyboard; a modem for connecting to a telephone line; buffer memory for receiving the entire digitized contents of a 2-dimensional viewing area; and, a first program for inputting telephone numbers, for establishing a connection to a receiving facsimile machine, for determining group type of the receiving machine, and for transmitting the digitized contents of buffer memory to the receiving machine in the proper format for its group type. When employed in the portable office, the system can be used as a photocopier to copy documents. The digitizing device can output digitized or OCR data.

Abstract: An origami printed circuit board comprises a rigid printed circuit board having a flexible conducting back secured to the bottom of the circuit board. The flexible back is constructed of alternating layers of flexible dielectric and conducting layers bonded together, where the conducting layers may include copper. The circuit board is then grooved in a predetermined manner with the grooves extending through the rigid circuit board, but not extending into the flexible conducting back. The entire circuit board/flexible back is then folded along the grooves in origami fashion to form an enclosure, or other designed shape, with the flexible back forming the outer walls of the shape. By coupling the electronic elements of the circuit board to the conducting layers of the flexible back, the flexible conducting back includes electronic circuit printed interconnections on the rigid board. A bottom conducting layer of the flexible back may be uncoupled to the electronic elements of the circuit board. When the origami printed circuit board is folded into shape, the bottom layer forms the board's outer wall and creates an EMI/TEMPEST shield. The shield also isolates RF frequency emissions.

Abstract: Many inertial navigation systems of both platform and ring laser strapdown types are currently in service. This paper discusses the possibility and desirability of incorporating a small GPS receiver in these systems. Advances in technology such as microprocessors, gate arrays, and surface mount devices allow the existing INS electronics to be replaced in a reduced volume. The remaining space in many cases is sufficient to permit the insertion of a small GPS receiver. Locating the GPS receiver in an inertial navigation system (INS) solves many of the usual system integration problems. Tight coupling between the GPS and INS can be achieved since data latency is minimized and well controlled. In such a configuration, rate aiding of the GPS is easily achieved. This approach also leads to greater flexibility and enhanced overall performance since all GPS and INS data are simultaneously available. While not providing the ultimate in redundancy, the integrated INS/GPS approach does offer greater simplicity with enhanced performance. This discussion primarily focuses on military systems. Nevertheless, the proposed techniques also are applicable to commercial units.

Abstract: For the testing of an integrated monolithic circuit (IC) the integrated monolithic circuit with a test bus which extends along a functional part of the circuit which is partitioned into macro circuits and which is coupled to the macro circuits, each macro circuit comprising a test interface circuit which is connected in series with test interface circuits of the other macro circuits; via the test interface circuits, the macro circuits can be coupled to the test bus. As a result, macro circuits can be separately tested and in the case of a hierarchic design of integrated circuits, utilizing previously designed marco circuits and test programs for previously designed macro circuits, test development times can be substantially reduced; this is an increasingly important aspect of increasingly complex circuits.

Abstract: Drivers, comparators, active loads, and per-pin timing circuitry for a VLSI test system are placed in two CMOS integrated circuits. This level of integration allows fast, low-capacitance pin electronics to be manufactured at relatively low cost. Novel design and calibration techniques are used to overcome limitations of CMOS technology. >

Abstract: A new test structure is described which allows full testing of highly complex Integrated Circuits. The test structure consists of a grid of externally as well as individually accessible probe-lines and sense-lines with electronic switches at the crossings of said probe and the sense-lines. One end of the switches is tied to an array of test-points on the IC that are to be either monitored or controlled during the testing, and the other end of the switches is tied to a sense-line. The ON and the OFF states of the switches are controlled by probe-lines. The probe and sense lines are connected to test electronics, thus permitting the test electronics to control the electrical signals on the probe-lines and to measure or apply signals on the sense-lines. Thus, by the excitation of an appropriate probe-line and the monitoring of an appropriate sense-line, the test signals present at any one of the test-points can be measured. Conversely, by the excitation of an appropriate probe-line and application of a test signal on another appropriate sense-line the electrical signal on any of the test-points can be externally controlled for the purpose of testing.

Abstract: In an optoelectronic integrated circuit, an electronic device is integrated with an optical device by fabricating the electronic device directly in a doped semiconductor layer of the optical device. The optical devices contemplated for use include at least a region of multiple low-doped or intrinsic quantum well layers; electronic devices include bipolar and field-effect transistors. Resulting integrated circuits exhibit a high degree of planarity.

Abstract: A wireless transmission method for power and data transmission, especially for a combined mechanically and electronically coded lock, uses power-supplied main electronics and part electronics with no power supply and with an energy storage circuit. Data and power transmission takes place respectively via coupling elements connected to the main electronics and part electronics. The power and data exchange is controlled by a microcontroller in the main unit in such a way that - power or data are transmitted alternately via the coupling elements, - the transmitted power is matched automatically to the consumption of the part electronics, including the transmission losses, by a variation of the power pulse length, - the starting times of the data sequences in the part electronics are synchronised with the cycles in the main electronics.

Abstract: Treats the scope of electronics design, encompassing both the fundamentals and tools available to designers. This revised edition covers more complex circuits, custom ICs, and CAD tools used in electronic circuit design.

Abstract: A system and method for its implementation for suppressing RFI effects on an electronic control module (10) enclosed in a metal housing (12) includes inserting a plurality of high frequency shunts (16, 26) in the wires (14) attached to the module (10) through the housing (12). The shunts (16, 20), comprising by-passing capacitors (21, 30) include one capacitor (21) on the incoming wire (14) disposed closely adjacent the housing (12) and grounded thereto and another capacitor (30) on each wire (14) disposed closely adjacent the connection of the wire (14) to the active circuit (11) of the module (10) and grounded to the circuit ground network (27). The housing (12) includes a direct connection (20) to ground and the ground network (27) for the electronic module (10) has a single ground connection (35) to the housing (12).

Abstract: Because of the increasing need for large area detectors the demand for integrated structures containing both detector and readout electronics becomes more relevant than ever. Nevertheless progress is rather limited, the main reason being the compatibility of integrated circuit and detector producing technologies. This paper discusses several alternatives for the practical realization of fully integrated detector-electronics circuits. The concept of full integration on high resistivity material is explored in detail and will be illustrated by experimental results.

Abstract: The article examines the implications of using light for the wiring functions within electronics processors, starting from the simple point-to-point fibre interconnect and following through to the 'all optical' computer and optical 'neural network'. In so doing, the strengths and weaknesses of optics are highlighted and some of the problems and opportunities established

Abstract: A novel method is presented for building high-performance pin electronics circuitry using conventional CMOS technology. To demonstrate the feasibility of these circuit techniques, a prototype processing-element chip consisting of four I/O channels was designed in a 2- mu m double-metal CMOS technology. It contains 13 K transistors in a die size of 3.9 mm*5.3 mm. Running at 33 Mvectors/s, the chip dissipates 125 mW with a 5-V supply. The authors feel that it is possible to build practical integrated pin electronics for functional VLSI testers with a technology only as good as that of the design under test. >

Abstract: A new type superconducting electronic device is described. In the description, a field effect semiconductor device is constructed in accordance with the present invention. A superconducting ceramic material is deposited on the source and drain regions of the semiconductor device with insulating film therebetween functioning as a tunnel current film.

Abstract: A hierarchical waveform-relaxation-based method for analysis of bipolar, MOS, and GaAs FET circuits is presented. By analyzing the circuit in a hierarchical manner, a faster solution has been obtained for circuits exhibiting strong bidirectionality and feedback than has previously been possible. The technique has been applied to a wide variety of digital and mixed analog/digital circuits, and circuits containing over 18000 transistors have been analyzed. Results obtained for a variety of circuits show up to two orders of magnitude improvement in computation time compared to conventional circuit simulation techniques and up to one order of magnitude improvement compared to the standard waveform-relaxation technique. >

Abstract: Material for GaAs integrated circuits digital integrated circuit design digital integrated circuit technologies monolithic microwave integrated circuit design monolithic microwave integrated circuit technologies GaAs sampled analogue integrated circuits heterojunction integrated circuits applications of GaAs integrated circuits.

Abstract: In this contribution a linear thermal model for hybrid circuits is presented. Both the heat dissipated in screen printed resistors and in mounted components such as transistors and integrated circuits is taken into account.

Abstract: An easily automated and heat-stable semiconductor contacting system for linear and planar SMD components, particularly LED arrangements. SMD components are applied to a carrier film coated with interconnects. The interconnects are entirely or partly formed of solderable material for simpler contacting through melting.

Abstract: The possibility of extending some of the logical methods that have been recommended for the design of software to the design of hardware, in particular, of synchronous switching circuits implemented in CMOS, is explored. The objective is to design networks that are known by construction. Things that can go wrong with circuits designed in this way are examined. The application of the techniques is discussed. >

Abstract: The invention is an improved integrated circuit chip assembly which provides enhanced heat transfer from active electronic devices of the integrated circuit by significantly reducing the thickness of the substrate and providing the necessary structural support through a thermally conducting spacing segment between the substrate and a ground plane in the region of the active electronic devices. This improvement further permits added flexibility in the design of transmission lines by permitting adjustment of the distance between the transmission line and the ground plane and furthermore by permitting the introduction of a second dielectric material such that the impedance of the transmission line may be controlled.

Abstract: It is important for the best use of optics and electronics to have an efficient and convenient means of converting between the two technologies. For example, it would be interesting to have optically interconnected electronic integrated circuits or two-dimensionally parallel optical processing systems in which electronic devices could be incorporated into processing nodes to provide increased functionality and improved system performance. To accomplish this effectively, it is crucial that the necessary components are integrated. We demonstrate here a method of integrating optical input and output devices with electronic components. Importantly, the input and output beams can be perpendicular to the chip so that 2-D interconnects are possible in principle, and the integration method is compatible with existing fabrication technology for the electronic devices.

Abstract: A description is given of the front-end electronics, which has been hybridized in order to accommodate high-packaging-density requirements. The hybrid package contains eight channels of amplifiers together with all the associated circuits for calibration, event recognition, and power-economy switching functions. A total of 1280 such hybrids are used. The amplifiers and associated circuits are described, and their performance is discussed. >

Abstract: In order to provide a through solar panels (1, 2, 3, 4) supplied with the energy required electric or electronic consumers (M) even under unfavorable lighting conditions and / or brief failures of the solar collector (S) continuously with the necessary electrical energy, a proposed electronics that between said solar panel (S) and the consumer (M) and a memory (C1) for electrical energy comprises a control circuit (RK), which acts at least as a supply and switches, the function of the voltage (US) at the solar panel (S) and a defined operating voltage (UM) at the load (M) and the state of charge of the memory (C1) by prioritizing the preparation of the operational readiness of the consumer (M) to the solar collector (S), the memory (C1) and the consumer ( M) interconnects. Characterized short-term failures of the solar collector (S) due to lack of sufficient light can be bridged on the one hand. On the other hand, can be avoided that the consumer (M) until there is enough electrical power available when the capacitor (C1) through the solar collector (S) to the operating voltage (UM) has been charged. The invention allows therefore to eliminate the disadvantages of the known solar-powered devices, and optimally utilize the light as an energy source for electrical consumers.