Electroetching

Abstract: Patterned copper structures are fabricated by selectively capping the copper employing selective etching and/or selective electroplating in the presence of a liner material. Apparatus for addressing the problem of an increased resistive path as electrolyte during electroetching and/or electroplating flows from the wafer edge inwards is provided.

Abstract: A tool and process for electroetching metal films or layers on a substrate employs a linear electrode and a linear jet of electrolyte squirted from the electrode. The electrode is slowly scanned over the film by a drive mechanism. The current is preferably intermittent. In one embodiment a single wafer surface (substrate) is inverted and the jet is scanned underneath. In another embodiment wafers are held vertically on opposite sides of a holder and two linear electrodes, oriented horizontally and on opposite sides of the holder, are scanned vertically upward at a rate such that the metal layers are completely removed in one pass. The process is especially adapted for fabricating C4 solder balls with triple seed layers of Ti--W (titanium-tungsten alloy) on a substrate, phased Cr--Cu consisting of 50% chromium (Cr) and 50% copper (Cu), and substantially pure Cu. Solder alloys are through-mask electrodeposited on the Cu layer. The seed layers conduct the plating current. During etching the seed layers are removed between the solder bumps to isolate them. The phased Cr--Cu and Cu layers are removed by a single electroetching operation in aqueous potassium sulfate and glycerol with cell voltage set to dissolve the phased layer more quickly than the Cu, avoiding excessive solder bump undercutting in the copper layer. The cell voltage may be such that the solder bump is only slightly undercut so as to form a stepped base C4 structure upon reflowing. Ti--W is removed by a chemical process.

Abstract: Etching processes are disclosed for producing a graded or stepped edge profile in a contact pad formed between a chip passivating layer (15) and a solder bump (10). The stepped edge profile reduces edge stress that tends to cause cracking in the underlying passivating layer (15). The pad comprises a bottom layer (14) of chromium, a top layer (12) of copper and an intermediate layer (13) of phased chromium-copper. An intermetallic layer (13) of CuSn forms if and when the solder is reflowed, in accordance with certain disclosed variations of the process. In all the variations, the solder (10) is used as an etching mask in combination with several different etching techniques including electroetching, wet etching, anisotropic dry etching and ion beam etching.

Abstract: Method of forming a multilayer structure by electroetching or electroplating on a substrate. A seed layer is arranged on the substrate and a master electrode is applied thereto. The master electrode has a pattern layer forming multiple electrochemical cells with the substrate. A voltage is applied for etching the seed layer or applying a plating material to the seed layer. A dielectric material (9) is arranged between the structures (8) thus formed. The dielectric layer is planarized for uncovering the structure below and another structure layer is formed on top of the first. Alternatively, the dielectric layer is applied with a thickness two layers and the structure below is accessed by selective etching of the dielectric layer for selectively uncovering the top surface of the structure below. Multiple structure layer may also be formed in one step.