Topic
Elastic interface bus
About: Elastic interface bus is a research topic. Over the lifetime, 2 publications have been published within this topic receiving 13 citations.
Papers
Patent•
IBM1
TL;DR: A double data rate elastic interface in which programmable latch stages provide an elastic delay, preferably on the driving side of the elastic interface, has been proposed in this article, but it is not limited to the driver side/chip, it can be implemented in the receiver side or chip as well.
Abstract: A double data rate elastic interface in which programmable latch stages provide an elastic delay, preferably on the driving side of the elastic interface. However, the invention is not limited to the driver side/chip, it can be implemented in the receiver side/chip as well. However, since the receiver side of an elastic interface already has complicated logic, the invention will be usually implemented on the driving side. The programmable latch stages on the driving chip side of the interface, can often operate at the local clock frequency (the same frequency as the elastic interface bus clock frequency), which in turn is half of the double data rate at which the receiving latch stages operate, thereby decreasing the logic and storage resources in the interface receivers. The programmable latch stages can also be used in the case that the local clock frequency is twice the elastic interface bus clock frequency.
10 citations
IBM1
TL;DR: In this article, a power noise compensation scheme consisting of a dynamic forwarded reference voltage, is proposed to provide an effective low-noise environment for the receiver threshold tolerance, which improves the overall performance of the Elastic Interface (El) bus.
Abstract: For high-speed signaling, differential channels are now commonly used because of the improved noise immunity and receiver sensitivity that can be achieved compared to the single-ended channels that had been widely used in electronic systems until recently. However, single-ended channels have the distinct advantage of only needing one signal trace per signal, which in a well-controlled impedance, low-noise environment can provide equivalent bandwidth per pin at a lower silicon area and lower power demand than differential signals. To provide an effective low-noise environment for the receiver threshold tolerance, a power noise compensation scheme consisting of a dynamic forwarded reference voltage, is proposed. This improves the overall performance of the Elastic Interface (El) bus [1], a single-ended high speed signaling technology used in IBM systems. We explore the range of voltage differences that could be observed at the transmit and receive circuits and how those differences can be mitigated to enhance the performance of the system. Simulations for channels with varying voltage characteristics confirm the anticipated performance improvement.
3 citations
Performance Metrics
| Year | Papers |
|---|---|
| 2009 | 1 |
| 2006 | 1 |