Effective resolution bandwidth

Abstract: We present a 6-bit 1.2-GS/s flash-ADC with wide analog bandwidth and low power, realized in a standard digital 0.13 /spl mu/m CMOS copper technology. Employing capacitive interpolation gives various advantages when designing for low power: no need for a reference resistor ladder, implicit sample-and-hold operation, no edge effects in the interpolation network (as compared to resistive interpolation), and a very low input capacitance of only 400 fF, which leads to an easily drivable analog converter interface. Operating at 1.2 GS/s the ADC achieves an effective resolution bandwidth (ERBW) of 700 MHz, while consuming 160 mW of power. At 600 MS/s we achieve an ERBW of 600 MHz with only 90 mW power consumption, both from a 1.5 V supply. This corresponds to outstanding figure-of-merit numbers (FoM) of 2.2 and 1.5 pJ/convstep, respectively. The module area is 0.12 mm/sup 2/.

Abstract: High-speed ADCs are key elements in the read channel of optical and magnetic data storage systems. The required resolution is about 6 b while the sampling rate (Fs) and effective resolution bandwidth (ERBW) requirements increase with each generation of storage system. Sample rates up to 800 MSample/s have been reported with ERBW=200 MHz. The ADC presented here achieves a maximum sample rate of 1.1 GSample/s and an EBBW of 450 MHz. This result is obtained with full flash interpolating/averaging architecture with distributed track-and-hold (T/H) in a standard 0.35 μm single-poly five-metal 3.3 V digital CMOS process. Chip area is 0.35 mm/sup 2/ and power consumption is 300 mW.

Abstract: A 10-b binary-weighted D/A digital-to-analog converter based on current division is presented. The effective resolution bandwidth is 5 MHz at a maximum clock frequency of 40 MHz. The circuit is integrated in a 0.8- mu m double-metal CMOS technology and the chip area is 0.4 mm/sup 2/. This particular converter was realized by constructing the bit currents through a careful combination of unit current sources and by limiting the driving voltage on the gates of the current switches. >

Abstract: This paper presents a 35-GS/s, 4-bit flash ADC-DAC with active data and clock distribution trees. At mm-wave clock frequencies, skew due to mismatch in the clock and data distribution paths is a significant challenge for both flash and time-interleaved converter architectures. A full-rate front-end track and hold amplifier (THA) may be used to reduce the effect of skew. However, it is found that the THA output must then be distributed to the comparators with a bandwidth greater than the sampling frequency in order to preserve the flat regions of the track and hold waveform. Instead, if the data and clock distribution have very low skew, the THA can be omitted thus obviating the associated nonlinearities and resulting in improved performance. In this work, a tree of fully symmetric and linear BiCMOS buffers, called a ldquodata treerdquo, distributes the input to the comparator bank with a measured 3-dB bandwidth of 16 GHz. The data tree is integrated into a complete 4-bit ADC including a full-rate input THA that can be disabled and a 4-bit thermometer-code DAC for testing purposes. The chip occupies 2.5 mm times 3.2 mm including pads and is implemented in 0.18 mum SiGe BiCMOS technology. The ADC consumes 4.5 W from a 3.3 V supply while the DAC operates from a 5 V supply and consumes 0.5 W. The ADC has 3.7 ENOB with a 3-dB effective resolution bandwidth of 8 GHz and a full-scale differential input range of 0.24 Vpp. With the THA enabled, the performance degrades rapidly beyond 8 GHz to less than 1-bit, but with the THA disabled, the ENOB remains better than 3-bits for inputs up to 11 GHz with an SFDR of better than 26 dB.