Dragon protocol

Abstract: Cryptographic techniques based on possession of private keys rely very much on the assumption that the private keys can be used only by the key's owner. As contemporary architectures of operating systems do not provide such a guarantee, special devices such as smart cards and TPM modules are intended to serve as secure storage for such keys. When carefully designed, these devices can be examined and certified as secure devices for holding private keys. However, this approach has a serious drawback: certification procedure is expensive, requires very specialized knowledge and its result cannot be verified independently by an end-user. On the other hand, malicious cryptography techniques can be used to circumvent the security mechanisms installed in a device. Moreover, in practice we often are forced to retreat to solutions such as generation of the private keys outside secure devices. In this case we are forced to trust blindly the parties providing such services. We propose an architecture for electronic signatures and signature creation devices such that in case of key leakage, any use of leaked keys will be detected with a fairly high probability. The main idea is that using the private keys outside the legitimate place leads to disclosure of these keys preventing any claims of validity of signatures in any thinkable legal situation. Our approach is stronger than fail-stop signatures. Indeed, fail-stop signatures protect against derivation of keys via cryptanalysis of public keys, but cannot do anything about key leakage or making a copy of the key by a service provider that generates the key pairs for the clients. Our approach is a simple alternative to the usual attempts to make cryptographic cards and TPM as tamper resistant as possible, that is, to solve the problem alone by hardware means. It also addresses the question of using private keys stored in not highly secure environment without a dramatic redesign of operating systems. It can be used as a stand alone solution, or just as an additional mechanism for building trust of an end-user.

Abstract: In this paper, snoopy cache coherence protocols with update strategy have been studied, since description of protocols is apparently different in references, so we offer a common description in order to show simplicity and comparability protocols. Evaluating of protocols is in simulation level By limes simulator tools. Limes includes dragon protocol [1], that we added WTU and firefly protocols to it. As the simulation results show, precision of block sharing information in multiprocessor system, is major reason for different performance of update snoopy cache coherence protocols, so if this information amount to be high, then performance will be high, but on the other hand, implementation cost will be high, as well.

Abstract: Configurable hardware accelerators offer the opportunity to execute compute intense parts of applications with a higher performance and a higher energy efficiency as in pure software execution. One important component in such accelerators is the memory access to the system memory. Typically, this is realized through a cache hierarchy. In this contribution, we implement two different cache coherence protocols in two different configurable HW accelerators on real hardware. Using multiple benchmarks, we evaluate the influence of the cache coherence protocol on the execution time of the accelerators. As a result, we show that the Dragon protocol performs better than the MOESI protocol.

Abstract: The data coherence in Chip Multiprocessors (CMPs) cache system is to be more accurate and reliable. A system with single producer and multiple consumers uses update based coherence protocol (dragon). This work proposes an effective solution for coherence verification in dragon through introduction of highly efficient test logic (fault detection unit). The test design is based on the modular structure of Cellular Automata (CA). The SACA (single length cycle single attractor cellular automata) has been introduced to identify the inconsistencies in cache line states of dragon. The simple hardware implementation of the CA based design realizes quick decision on the cache coherency in CMPs with 100% accuracy.