TL;DR: The implementation in the IBM zEnterprise EC12 (zEC12) microprocessor generation, focusing on how transactional memory can be embedded into the existing cache design and multiprocessor shared-memory infrastructure, is described.
Abstract: We present the introduction of transactional memory into the next generation IBM System z CPU. We first describe the instruction-set architecture features, including requirements for enterprise-class software RAS. We then describe the implementation in the IBM zEnterprise EC12 (zEC12) microprocessor generation, focusing on how transactional memory can be embedded into the existing cache design and multiprocessor shared-memory infrastructure. We explain practical reasons behind our choices. The zEC12 system is available since September 2012.
TL;DR: A collection of DNA sequence analysis programs, called "PC Sequence" (PCS), which are designed to run on the IBM Personal Computer (PC), and take full advantage of the IBM PC's speed, error handling, and graphics capabilities.
Abstract: We present here a collection of DNA sequence analysis programs, called "PC Sequence" (PCS), which are designed to run on the IBM Personal Computer (PC). These programs are written in IBM PC compiled BASIC and take full advantage of the IBM PC's speed, error handling, and graphics capabilities. For a modest initial expense in hardware any laboratory can use these programs to quickly perform computer analysis on DNA sequences. They are written with the novice user in mind and require very little training or previous experience with computers. Also provided are a text editing program for creating and modifying DNA sequence files and a communications program which enables the PC to communicate with and collect information from mainframe computers and DNA sequence databases.
TL;DR: A block erasable flash memory provides the capability of BIOS updates while providing boot and recovery code protected from inadvertent program or erasure, and is an ideal storage medium for PC and notebook computer BIOS code.
Abstract: The author describes a flash memory device used to store the basic input/output system (BIOS) of a PC or notebook computer. Rapidly increasing computer complexity requires rapid and convenient BIOS modifications. BIOS code can be stored in ROM, EPROM, EEPROM, bulk erasable flash memory, or block erasable flash memory. Updating BIOS stored in ROM or EPROM requires much time and money. BIOS storage does not require EEPROM's feature of byte erasure. Rapid and inexpensive BIOS revisions can be accomplished in flash memory with update software provided on a desk or by modem. Block erasable flash memory provides the capability of BIOS updates while providing boot and recovery code protected from inadvertent program or erasure. BIOS code is easily updated in flash memory containing an internal program and erase sequence controller. A 1-Mb block erasable flash memory with an internal program and erase sequence controller is an ideal storage medium for PC and notebook computer BIOS code. >
TL;DR: In this paper, the authors describe a personal computer system which includes a central processing unit (CPU) coupled to a direct access storage device (DASD), a random access memory (RAM), and a LAN controller.
Abstract: Disclosed is a personal computer system which includes a central processing unit (CPU) coupled to a direct access storage device (DASD), a random access memory (RAM), and a LAN controller. A flash memory module is coupled to the CPU and an input/output (IO) bus and includes a basic input output system (BIOS) stored therein. The BIOS is effective for responding to the energization of the computer system by initiating a power on self test (POST). The BIOS is further operative on completion of the POST for transferring a portion of BIOS from the module to the RAM and for transferring control of the of the computer system to the BIOS portion. The portion of BIOS is operative to load a protected mode operating system (OS) into RAM and transfer control to the OS. The system further includes a logic circuit coupled to the flash memory module and the IO bus. A communication subsystem is coupled to the IO bus, the logic circuit and the flash memory for allowing the remote computer to access the BIOS in flash memory while the protected mode OS is running.
TL;DR: This application note describes various methods of implementing a flash memory BIOS using Intel's 28F001BX, with primary emphasis on application of flash memory for BIOS and ROM executable software applications.