Abstract: A discrete-time model is presented of memory interference in multiprocessor systems using multiple-bus interconnection networks. It differs from earlier models in its ability to model variable connection time and arbitrary inter-request time. The model describes each processing element's behavior by means of a semi-Markov process, taking as input the number of processing elements, the number of memory modules, the number of buses, the mean think time of the processing elements, and the first and second moments of the connection time between processing elements and memories. The model produces as output the memory bandwidth, processing element utilization, memory module utilization, average queue length at a memory, and average waiting time experienced by a processing element while waiting to access a memory. Using the model, it is possible to analyze the interaction of the input parameters on the system performance without using a complex Markov chain; a four-state semi-Markov process is sufficient regardless of the think and connection time distributions. The accuracy and capability of the model are illustrated.

Abstract: Disclosed is a multiprocessor computer system including a plurality of processor modules with each of the processor modules including at least one processor and a cache memory which is shared by all of the processors of each processor module. The processor modules are connected to a system bus which comprises independent data, address, vectored interrupt, and control buses. A system memory which is shared by all the processor modules is also connected to the buses, and the cache memories in each processor module store those memory locations in the main memory most frequently accessed by the processors in its module. A system control module controls the operation and interaction of all of the modules and contains the bus arbiters for the vector, data and address buses. The system control module also controls the retrying of requests which are not completed and should any requester fail to obtain access to a bus, the system control module also unjams this deadlock. Each of these multiprocessor computer systems can be connected to another multiprocessor computer system through an interface which includes a cache for housing frequently accessed locations of the other multiprocessor system.

Abstract: Simulation is one example of an application that shows great potential benefits from distributed processing The conventional approach to simulation, that of sequentially processing the events, does not exploit the natural parallelism existing in some simulation models This is particularly true in large models, where submodels often interact weakly and can be simulated in parallel The decreasing cost of multiprocessor systems also suggests that a distributed approach to simulation can be workable Moreover, such an approach can be very attractive, since time and memory limitations, often major constraints with simulation programs, may be alleviated by distributing the load among several processors Distributed simulation requires a set of processors that can communicate by sending messages along the links of a communication network or via a shared memory The processors each simulate a submodel of the overall model and interact when necessary Submodel interactions produce the interprocessor communication in the simulator Two methods for distributed simulation are studied in this thesis Both methods are applicable to discrete time simulation models and are fully distributed in the sense that they require no central control In one method, each processor can simulate independently as long as it is certain that no events will arrive that belongs to the past of the simulation process In the second method, processors are not concerned about future arriving events They simulate independently and roll back if an event arrives that belongs to the past The thesis consists of two parts The first presents some centralized and distributed algorithms for efficient utilization of the second method The issue of load balancing is also discussed in this part and some heuristic algorithms are presented The second part of the work consists of mathematical modeling and analysis of models of both methods The analysis gives some insight into the effects of different system parameters on the performance The performance of each method is compared with the other and also with single processor simulation The mathematical models are then confirmed and complemented with the simulation results Finally, results of the implementation of the second method are presented

Abstract: Memory interleaving and multiple access ports are the key to a high memory bandwidth in vector processor systems. Each of the active ports supports an independent access stream to memory among which access conflicts may arise. Such conflicts lead to a decrease in memory bandwidth. The authors present some analytical results for the calculation of the resulting effect bandwidth for one and two access streams to a memory system in a vector processor. In particular, conditions for conflict-free access are given together with some conflicting cases that should be avoided. Finally, examples of measurements on a Cray X-MP and corresponding simulations are presented.

Abstract: An improved method for communicating updated information among processors in a distributed data processing system. The system includes a plurality of distributed interconnected processors each having a memory. The method includes the steps of prioritizing the processors into a predetermined order, establishing one of the processors as a control processor for the broadcast of update messages, developing an update message in at least one of the processors, selecting in accordance with the control processor one of the processors which has developed an update message as a sender processor, broadcasting the update message of the sender processor to each of the processors, and causing the next processor in order to be selected as control processor in the event that the former control processor fails in service. As one preferred use, the method enables the system to transmit atomic global update messages with a tolerance to multiple processor faults.

Abstract: A fault tolerant data processing system includes a pair of processors for simultaneously executing commands for processing data, a memory, and a data transmission bus between the processors and the memory voer which the processors may fetch data from and write data to the memory. A comparison circuit is included between the processors for comparing the data fetched and written by the processors. A rollback module is responsive to the comparison circuit for rolling back the operation of the processors to the beginning of a presently executing command in the event of a miscomparison by the comparison circuit.

Abstract: A digital computer including a plurality of memory elements, the memory elements being interleaved (i.e., each is assigned memory addresses on the basis of a low order portion of the memory address), a plurality of processors connected in parallel, the processors each having means for initiating an access of data from any of the memory elements simultaneously with accesses of other processors, the memory elements each being capable of accepting an access from just one of the processors during a given cycle, and the memory elements being interleaved so that the memory access patterns generated at a stride of one and a stride of two each meet the conditions that (1) the pattern will tolerate being offset with respect to an identical pattern by a desired offset and any multiple of the offset (wherein tolerating means that no memory access conflicts arise, i.e., more than one processor simultaneously attempting to access the same memory element) and (2) the pattern includes sufficient conflicts at offsets other than the desired offset to force the processors to assume a relationship wherein the desired offset is achieved, so that the processor is able to access a different memory element simultaneously without creating access conflicts.

Abstract: A multiprocessor data processing system in which a number of independent processors can concurrently operate on a shared memory even when one processor is performing a read-modify-write (RMW) operation, the system having a locking, content-associative write buffer and a controller for identifying RMW requests, for addressing the buffer and, for issuing directives to lock the buffer, to validate particular data blocks in the buffer and to transfer data back and forth between the processors, the memory and the buffer.

Abstract: A system and method for processing an extraordinarily large amount of data is configured using ordinary versatile computers of relatively slow data processing speed. Tasking is shared to plural computers or processors connected to a system bus; a shared storage device provided in common for these processors is made up of plural memory banks connected to the system bus; data transferred between the processors and the memory banks are divided into a predetermined amounts of divisional data; the data are processed for each divisional data simultaneously in parallel fashion; and each memory bank is occupied simultaneously in parallel fashion in response to each memory request from each processor. An arbitrator is provided for acting on a single memory request in accordance with a predetermined priority order in the case where plural memory requests are outputted simultaneously to the same memory bank.

Abstract: A network interface equipment for a bus network employs separate processors and random-access memories for handling bus-protocol and data portions of a data packet. Each processor has access to a separate random-access memory to and from which it moves data. The random-access memories are multiple-ported to permit access by more than one requester with a logic arbitrator to resolve conflicts. A status random-access memory provides communication between the two processors.

Abstract: A memory interface and conflict resolution network for a multiprocessor system. The memory is multisectional and each section of memory has a plurality of individually addressable memory banks organized in an interleaved fashion and a section level conflict resolution network. Each processor in the system includes several ports and a gating network such that each port may access any section of memory, but access is restricted to no more than one reference per processor per clock period to each section of memory. References generated from different ports of the same processor are automatically synchronized. Each processor has a conflict resolution circuit to resolve conflicts between different ports seeking access to the same section of memory. Conflict resolution is achieved in two clock periods with conflicts between different ports of a processor resolved in the first clock period and conflicts between different processors seeking access to the same banks of any particular section of memory resolved in the second clock period.

Abstract: An arbitration system for a machine tool control has multiple processors and a local memory associated with each processor The arbitration system allows one processor to access data stored in a foreign memory, ie the local memory of a second processor so that the time required for one processor to gain access to data used by another processor is relatively short The system includes an external arbitration control which arbitrates requests for access to a foreign memory from each of the processors The system also includes a plurality of local arbitrators each associated with a particular processor to arbitrate requests for access to its processor's bus and memory from a plurality of users including the external arbitration control, a DRAM controller and a direct memory access controller

Abstract: A system for sharing several memory modules by several processors on a common bus uses a protocol in which, after a processor gains access to a memory module read or write data is transferred on the bus within a preset number of system clock periods. After priority is established by polling, the processor sends memory address on the common bus. For each operation several idle system clock periods are provided before data is returned from the memory to permit the memory to retrieve the data. Meanwhile, the protocol interleaves requests for access to other memory modules from other processors thereby increasing the throughput of the system.

Abstract: Much of the work to date on distributed systems has focused on the correct choice of communication paradigm, stressing (for example) message primitives, remote procedure call, problem- oriented protocols and so on. A distributed system service is then implemented as a module executing on particular server machine that is accessed using these communication facilities. In contrast, the shared memory paradigm has been used on multiprocessor and uniprocessor systems. In the shared memory paradigm, the state of a service is stored in shared memory and implemented in a decentralization fashion across multiple processors using this shared memory.This paper describes some preliminary thoughts on applying the shared memory paradigm to distributed systems. For efficiency reasons, shared memory is not provided in its full generality, but only with the semantics required for the applications of interest. This type of application-specific memory is called a problem-oriented shared memory. The use of problem- oriented shared memory is illustrated by describing several applications we are exploring in the V distributed system. We also discuss basic requirements on a communication system to support this approach.

Abstract: This paper describes the design of the hardware and software for a multiprocessor, silicon memory, database machine—the SiDBM. The entire database resides in stable silicon memory; there are no disks. The processors are functionally specialized, with relation managers, host interfaces, query managers, and query processors. The processors are tightly coupled, and the silicon memory is shared and is directly addressable by all of them. The SiDBM supports a relational model, and allows concurrent transactions and queries. The number of processors and the database size can be selected to suit the application; the expected range is 3 to 16 processors, and 100 megabytes to 2 gigabytes of data. This paper also gives some preliminary performance results for the SiDBM.

Abstract: In order to provide high performance computing, the development of large scale multiprocessors is desirable. In the past, the performance of such processors has been substantially reduced by switching delays in the interconnection network and the inability to effectively use private caches due to cache coherency problems. Meanwhile the design and development of such systems has been hindered by the large amount of time required to simulate large multiprocessors. This thesis proposes solutions to both problems, through a new family of multiprocessor architectures and new techniques for large system simulation. The multiprocessor architectures are based on the use of private, write-deferred caches with distributed multicache coherency control which take advantage of the broadcasting ability inherent in shared bus interconnection networks. The thesis develops methods to extend the distributed coherency control scheme to networks of multiple, hierarchical shared buses, thus allowing even larger systems. The extended coherency control uses hierarchical caches as "coherency guardians" for groups of private caches. The hierarchical shared bus interconnection network allows direct access from all of the processors to all of the memory locations. The thesis analyses several specific architectures which incorporate the extended coherency control and concludes that a cluster approach with distributed memory is best. The hierarchical simulation methodology developed in this thesis significantly reduces the amount of time required to simulate large multiprocessor architectures. The architectures are divided into a hierarchy of subsystems, with each subsystem simulated in detailed. The simulated subsystem behavior is then used when simulating the next higher level subsystems. The thesis demonstrates that reductions in simulation time of two orders of magnitude are possible. The thesis proposes methods for statistically capturing the behavior of subsystems as part of the recursive simulation strategy. Comparisons with direct simulations are performed which show that the statistical methods maintain good fidelity. Thus the new simulation methodologies are shown to be both accurate and efficient. Using the hierarchical simulation methodology, the thesis demonstrates that the proposed architecture is capable of nearly linear speedup for systems composed of over 100 processors. It is found that the extended cache coherency control system produces little overhead, and that hierarchical caches can further reduce global bus bandwidth requirements.

Abstract: : Incremental garbage collection schemes incur substantial overhead which is directly translated as reduced execution efficiency for the user. Parallel garbage collection schemes implemented via time-slicing on a serial processor also incur this overhead, which might even be aggravated due to context switching. It is useful, therefore, to examine the possibility of implementing a parallel garbage collection algorithm using a separate processor operating asynchronously with the main list processor. The overhead in such a scheme arises from the synchronization necessary to manage the two processors, maintaining memory consistency. In this paper, we present an architecture and supporting parallel garbage collection algorithms designed for a virtual memory system with separate processors for list processing and for garbage collection. Each processor has its own primary memory; in addition, there is a small common memory which both processors may access. Individual memories swap off a common secondary memory, but no locking mechanism is required. In particular, a page may reside in both memories simultaneously, and indeed may be accessed and modified freely by each processor. A secondary memory controller ensures consistency without necessitating numerous lockouts on the pages. (Author)

Abstract: In the very large multiprocessor systems and, on a gander scale, computer networks now emerging, processes are not tied to fixed processors but run on processors taken from a pool of processors. Processors are released when a process dies, migrates or when the process crashes. In distributed operating systems using the service concept, processes can be clients asking for a service, servers giving a service or both. Establishing communication between a process asking for a service and a process giving that service, without centralized control in a distributed environment with mobile processes, constitutes the problem of 1 distributed matchmaking. Logically, such a match-making phase precedes routing in store-and-forward d6mputer networks of this type. Algorithms for distributed match-making are developed and their complexity is investigated in terms of message passes and in terms of storage needed. The heoretical limitations of distributed matchmaking are established, and the techniques are applied to several network topologies.

Abstract: In this correspondence, we study the performance of a multiprocessor in which a crossbar is employed to interconnect p processors to m commonly shared memory modules. A set of nonuniformly distributed probabilities including a probability P(0) which denotes the probability of a processor not generating any request is also employed to illustrate the program behavior, but no distinction is made between processors. Several relations between the average request completion time, the average processor utilization, and the effective memory bandwidth are obtained. One approximation method based on the idea of aggregation is proposed. Its solutions are compared to the exact solution.

Abstract: Multiprocessor system with a common multiplexor (3) and a common memory (4) operating asynchronously. To this effect, the multiplexor releases according to the demand of the processor (1, 2) a corresponding transceiver (7, 8) for the data and an address memory (5, 6) for the address. A priority coder (9) insures that only one processor at a time has access to the common memory.

Abstract: The architecture and instruction set of a second-generation VLSI digital signal processor are described. This processor represents a significant advance in VLSI digital signal processors. The device may be differentiated from its predecessors by the fact that it more closely resembles a true microprocessor than other DSP microcomputers. Its multiprocessor capabilities further distinguish it, allowing for much more flexibility in overall system design. The architecture of the device allows a dual bus structure to be maintained on-chip, while external bus hardware requirements are minimized via the multiplexing of these busses externally. Some of the notable features incorporated onto the device include two large on-chip RAM blocks, large external program/data address spaces, single-cycle multiply/accumulate instructions, hardware and instructions for efficient memory management, and a versatile multiprocessor interface.

Abstract: Many industrial applications require the use of multiple computing elements. The overall performance of such multiprocessor systems is a strong function of the communication capacity of the interconnection bus. By increasing this capacity one can integrate more processors, memory units, and input-output devices together and obtain a higher overall system throughput. In this paper, an analytic model is used to analyze alternative bus architectures. Both the local memory and global memory cases are analyzed; the instance in which the global memory case can be simplified is identified. Finally, the overall impact of implementing queues to increase computational throughput is analyzed.

Abstract: A discrete time model of memory interference in multiprocessors is developed. The model, termed the semi-Markov memory interference model, explicitly describes the behavior of each processing element by means of a semi-Markov process. The model requires as input the number of processing elements and the number of memory modules in the multiprocessor, the mean think time of the processing elements, the first and second moments of the connection time between the processing elements and the memories, and the probability mass function characterizing the destination of the requests for memories of the processing elements. The model produces as output the memory bandwidth, processing element utilization, memory module utilization average queue length at a memory, and average waiting time experienced by a processing element while waiting to access a memory. Thus, it is possible to analyze the interaction of variable connection time, think time and the distribution of the destination of the memory requests on the system performance. This modeling capability is attained without having to employ a complex Markov chain. Indeed, the number of states in the semi-Markov process describing a processing element is dependent only on the probability mass function describing the destination of the memory requests. For instance, in the simplest and most common case when requests are directed with equal probability to each memory module, a four state semi-Markov process is sufficient regardless of the think and connection time distributions. The accuracy and capability of the model is demonstrated by comparing the results of the model with simulation. Moreover, the performance of a multiprocessor system with cache memories is analyzed using the model which assumes that the interconnection network can be a full crossbar network or a multiple-bus network.

Abstract: One aspect of network design is the extent to which memory is shared among the processing elements. In this paper a model with limited sharing (only two processors connected to each memory) is analyzed and its performance compared with the performance of two other models that have appeared in the literature. One of these is a model of multiple processors sharing a single memory; the other model considers a multiprocessor configuration in which each processor has its own dedicated memory. The tasks processed by these networks are described by both time and memory requirements. The largest-memory-first (LMF) scheduling algorithm is employed and its performance with respect to an enumerative optimal scheduling algorithm is bounded. On the basis of this measure we conclude that memory sharing is only desirable on very small networks and is disadvantageous on networks of larger size.

Abstract: : The CRAY X-MP 2- and 4-processor memory systems are analyzed and simulated using an instruction-level timing simulation of up to 16 processors. This study indicates a disturbing counter-intuitive trend to longer delays in vector accesses as both the number of processors and memory banks increase proportionately. This delay appears to be related to access start-up delays, which are determined for various memory organizations. Keywords include: Supercomputers; Simulation; and Parallel processors.

Abstract: A nodular, expandable, topologically-distributed-memory multiprocessor computer comprises a plurality of non-directly communicating slave processors under the control of a synchronizer and a master processor. Memory space is partitioned into a plurality of memory cells. Dynamic variables may be mapped into the memory cells so that they depend upon processing in nearby partitions. Each slave processor is connected in a topologically well-defined way through a dynamic bi-directional switching system (gateway) to different respective ones of the memory cells. Access by the slave processors to their respective topologically similar memory cells occurs concurrently or in parallel in such a way that no data-flow conflicts occur. The topology of date distribution may be chosen to take advantage of symmetries which occur in broad classes of problems. The system may be tied to a hose computer used for data storage and analysis of data not efficiently processed by the multiprocessor computer.

Abstract: Publisher Summary This chapter presents different characteristics of human memory. Human memory is at present believed to be a complex system of independent storage systems with a central large capacity store called long-term memory (LTM). Human memory can be characterized as a collection of stores with different characteristics. LTM employs a semantic code and stores material in a highly organized manner. Retrieval from LTM is often a process of reconstruction rather than the output of information held in LTM. This contrasts strongly with most machine memories that are usually simple depositories of information where one only gets out what one puts in. With human memory, on the other hand, one gets out what the memory system itself puts in. Memory is a major limitation on human performance and the designer should always think about the load his system imposes on the user. To lessen this load, it is necessary to allow for the characteristics of the various stores involved. Thus, long term memory will only effectively encode material that is meaningful to the user and the designer must ensure that the model the user constructs of the system is compatible with his own. If relatively meaningless material must be remembered temporarily, then knowledge of the characteristics of short term memory is relevant.