Abstract: A multiprocessing three level memory hierarchy implementation is described which uses a "write" flag and a "share" flag per page of information stored in a level three main memory. These two flag bits are utilized to communicate from main memory at level three to private and shared caches at memory levels one and two how a given page of information is to be used. Essentially, pages which can be both written and shared are moved from main memory to the shared level two cache and then to the shared level one cache, with the processors executing from the shared level one cache. All other pages are moved from main memory to the private level two and level one caches of the requesting processor. Thus, a processor executes either from its private or shared level one cache. This allows several processors to share a level three common main memory without encountering cross interrogation overhead.

Abstract: A new proposal for synchronization and communication in parallel programs is presented. The proposal, called synchronization resources, combines and extends aspects of procedures, coroutines, monitors, communicating sequential processes, and distributed processes. It provides a single notation for parallel programming with or without shared variables and is suited for either shared or distributed memory architectures. The essential new concepts are operations, input statements, multiple processes and resources. The proposal is illustrated by solving a variety of parallel programming problems. Key Words and Phrases: parallel programming, processes, synchronization, process communication, monitors, distributed processing, programming languages, operating systems, data bases. CR Categories: 4.20, 4.22, 4.32, 4.35

Abstract: Multiprocessor arrays have the property of regularity, enabling a low-cost VLSI implementation. However, multiprocessor systems with a fixed structure tend to be error prone and restricted to specialized applications, which makes them less attractive to the semiconductor industry. Consequently, reconfigurability and fault-tolerance are desirable features of a multiprocessor array. A multiprocessor array with a flexible structure can be adapted to many applications and may restructure itself upon failure of a processor, to avoid using faulty processors.The objective of this work is to demonstrate the feasibility of a multiprocessor array having these properties. An example of such an array is introduced, and distributed structuring algorithms for it are presented. A novel strategy for internal testing and for identification of faulty processors is developed, and the structuring algorithms are modified to accommodate faulty processors.

Abstract: A data communication arrangement in which an interface processor effects the transmission of messages between two processors of a multiprocessor system. The interface processor is connected to the communicating processors via direct memory access circuits. A sending processor stores messages in a send buffer in memory of the sending processor and controls a pointer in that memory indicating the loading of message into that buffer. The interface processor reads this pointer and the messages, and writes a pointer and the messages in a receive buffer of a receiving processor. The interface processor limits the loading of new messages into the send buffer by delaying the updating of an unload pointer, creating memory space for new messages, until the receiving processor has processed the transmitted messages. Messages can also be used to initiate the transfer of a block of data from the memory of one processor to that of another. Initialization of the interface processor is a joint effort of the communicating processors.

Abstract: Apparatus for regulating access by each of a plurality of asynchronous data processors to each of a plurality of memories, each processor being associated with one of the memories and needing both read and write access to its own memory and to the processor's memories, the apparatus including local bus circuitry to selectably permit each processor to have, or to prevent each processor from having, access to its associated memory, connecting bus circuitry to selectably permit each processor to have, or to prevent each processor from having, direct access to the other processors' memories, and control circuitry for giving each requesting processor access over the connecting bus to another processor's memory, and for giving each processor access over the local bus circuitry to its own memory except when access to its own memory is being given to another one of the processors.

Abstract: In this paper we describe a new family of topologies for interconnecting many identical processors to form an MIMD multiprocessor. It extends to arbitrarily many processors while keeping the number of neighbors of any one processor fixed. We show that this family behaves very well with respect to uniformity of bus load, simplicity of routing algorithms, and distance between processors.

Abstract: : This paper describes the connection memory, a machine for concurrently manipulating knowledge stored in semantic networks. We need the connection memory because conventional serial computers cannot move through such networks fast enough. The connection memory sidesteps the problem by providing processing power proportional to the size of the network. Each node and link in the network has its own simple processor. These connect to form a uniform locally-connected network of perhaps a million processor/memory cells. (Author)

Abstract: A computer arrangement for facilitating the sharing of information among computers at a memory level. Each computer includes means for accessing the main memory of another computer of the complex at machine word level, means for transmitting an interruption instruction from itself to the arithmetic control unit of the other computer, means for detecting a problem in the arithmetic control unit of itself, and means for altering one section of the logic address viewed from itself to some of a plurality of physical address spaces such as to make the same the logic address of a shared information storage region of the computer complex viewed from the program of each of the member computers. Shared information required for each computer is stored in its own main memory. When a problem occurs in the computer having the aforesaid shared information storage region it becomes evident in the computer's arithmetic control unit. As a result, an interruption instruction is sent to each of the other computers. The computers receiving the interruption permit the shared information stored in their own main memories to be transferred through the access enabling means to the main memories of the other computers to be written therein thereby restoring the shared information storage region, and permitting continual data processing.

Abstract: A digital data processor comprises a high speed processor (50) having input ports (52) and output ports (54), a memory (56), and a slow speed support processor (58), the memory being accessible to both the high speed and slow speed processors. The high speed processor can effect processing in dependence upon parameters written into the memory by the slow speed processor and which may have been derived by analyzing data supplied to the slow speed processor from the high speed processor via the memory.

Abstract: The flexibility afforded by multiprocessor systems opens the question of how to assign computer program modules among functionally similar processors in a distributed computer network. In the model under consideration, the modules of a program are to be assigned among processors in such a way as to minimize interprocessor communication while taking advantage of affinities of certain modules to particular processors. The problem is formalized as a zero-one quadratic programming problem, and a solution is sought through an iterative technique that performs a series of transformations on an assignment matrix. Convergence to a locally optimum assignment is guaranteed, and an easily testable condition is given for which this local optimum is also a global optimum. An illustration of this algorithm is provided, results of performance experiments are reported, and suggestions are made for further study.

Abstract: Several interprocessor communication mechanisms for multiprocessor systems have been proposed. An efficient communication scheme must facilitate high throughput and good response time. We introduce such an efficient scheme, describe the hardware involved, and evaluate its performance. The method is based on a compile-time tagging of shared data and on using different paths for “shared” (S-) and “private” (P-) data. The S-data accesses a shared cache on a word-by-word basis; the P-references are made to a local memory under a demand paging system. The resulting design avoids most shortcomings of other communication methods and supports multiprogrammed multiprocessor systems.

Abstract: : This dissertation deals with two related problems: development of a methodology for achieving memory and computation efficiency of computer programs, and the use of this methodology in very high-level programming and associated automatic program generators. Computer efficiency of programs has many aspects. Usually additional memory saves computation by avoiding the need to recompute certain variables. Our emphasis has been on reducing memory use by variables sharing memory space, without requiring recomputation. It will be shown that this also reduces computation overhead. The most significant savings are due to sharing memory in iterative steps. This is the focus of the reported research.

Abstract: A computer architecture for concurrent computing is proposed that has the shared memory aspect of tightly coupled multiprocessor systems and also the connection simplicity associated with message-connected, loosely coupled multicomputer systems. A large address space is dynamically partitioned into contiguous segments that can be accessed by a single processor. The partitioning is accomplished by switching the system buses, using semiconductor switches. The completion of a concurrent process is signaled by a processor's return to an idle state and the reattachment of its memory segment to the neighboring active processor. In effect, the assignment of an address sequence and the activation of a processor is a process FORK operation, and the processor deactivation and memory segment reattachment is a process JOIN. Following a description of the MP/C structure and basic operation, some additional enhancements of the system, which improve the applicability of MP/C to many classes of computations, are outlined. Applications include tree-structured multiprocessing, recursive and nondeterministic procedures, arbitrary concurrent computations, very high precision numeric calculations, and process-structured operating systems. The linear MP/C structure is extensible to higher dimensions. A two-dimensional system is described, and its usefulness for data base operations and array processing is discussed.

Abstract: Cache memory has played a significant role in the memory hierarchy and has been used extensively in large systems and minisystems. The effectiveness of cache memories with alternative main memory update policies in a multiprocessor system is a major concern in this paper. The performances of write-through with write-allocation or no-write allocation, buffered write-through, flag-swap, and buffered flag-swap policies have been analyzed. Because of the dominating cost of the interface between processors and main memory modules in the multiprocessor system, the effect of varying the bus width or block size has also been considered. Queuing models were developed to analyze these alternative organizations, and results predicted by the models were validated by a set of simulations.

Abstract: A possible design alternative to improve the performance of a multiprocessor system is to insert a private cache between each processor and the shared memory. The caches act as high-speed buffers, reducing the memory access time, and affect the delays caused by memory conflicts. In this paper, we study the performance of a multiprocessor system with caches. The shared memory is pipelined and interleaved to improve the block transfer rate, and assumes an L-M organization, previously studied under random word access. An approximate model is developed to estimate the processor utilization and the speedup improvement provided by the caches. These two parameters are essential to a cost-effective design. An example of a design is treated to illustrate the usefulness of this investigation.

Abstract: A distributed computer system environment for executing extended abstract data flow graphs (EDFGs) is presented. Sequencing functions in EDFGs depends on the availability of data. Since the functions are free of side effects, unrelated functions can be executed in parallel if the required data is available.The environment comprises an organization of conventional or data flow processors and the kernel functions of a distributed operating system. The processors are organized in groups, or levels. Each level is for executing the unrelated functions, or nodes, of EDFGs that are at a certain path length. Each node of an EDFG executes on a processor except when the node is to be replaced by a graph. The processors need not be identical in terms of physical characteristics. For each level of processors there is a memory unit, called level-i memory, with which the processors communicate. There is also a system memory with which all the levels can communicate. The system memory is a tagged memory containing data that can be useful to several levels.The communication between processors and other components is asynchronous, using an abstract data flow protocol. This asynchronous communication is supported by a message switcher. Each level has interconnection networks for connecting processors at that level, for processors and the level-i memory unit, and for processors and the system memory unit. The processors at each level are partitioned into two domains so that operating system programs and application programs can be simultaneously executed. The processors in the problem domain are called application processors (APs); those in the supervisor domain are called supervisor processors (SPs). Two classes of interconnection networks for connecting processors in level i are discussed. The first class of interconnection networks is intended for situations where any healthy processor can be designated as AP or SP. The second class of interconnection networks is intended for situations where only a subset of the processors can be used as APs. The rest of the processors are intended for SPs.The execution of EDFGs on the above organization of processors requires an operating system to map nodes in EDFGs to processors, to assure smooth flow of data into and out of processors, to measure performance, and to diagnose faults. The kernel functions of a distributed operating system are presented. The kernel functions are replicated for each level of processors to facilitate the autonomous functioning of processors in each level and cooperation with other levels using the abstract data flow protocol. The communication between the kernel functions is also asynchronous, using the abstract data flow protocol.

Abstract: The letter presents a multiprocessor system particularly advantageous in tightly coupled structures. The procedure is based on the fact that the microprocessor CPUs actually interact with the memory and I/O devices during a small fraction of the clock cycle. Conflicts in the memory bus access are avoided by a simple clocking and enabling method.

Abstract: PURPOSE: To speed an interchange of data without varying the period of access to the common memory of processors, by shifting the timing of access to the common memory. CONSTITUTION: On the basis of input data, a processor 1 performs numeric control processing under the control of a control program stored in a memory 4, and then writes the result in a common memory 3. A processor 2, on the other hand, reads instructions stored in the memory 3 from the processor 1 and a performs sequence processing on the basis of a sequence proram stored in its own memory 5 to output the processing result to a receiver and driver 6, controlling a machine. A timing control circuit 7 controls the timing of access to the common memory 3 of the processors 1 and 2. COPYRIGHT: (C)1982,JPO&Japio

Abstract: The described multiprocessing system uses only one kind of microprocessoras a common intelligent element in order to offer faster response with greater throughput. Unusual design features overcome some of the drawbacks which limit other multiprocessing architectures. A hierarchy of buses allows communication among the master processor, the subordinate processors, and local modules within a subordinate processors, and local modules within a subordinate processor. A flexible set of address mappings allows processors to access the distributed memory. Subordinate processors have two distinct address mappings in order to make different memory regions available on the various buses. The resulting high performance architecture is easily customised for a variety of applications.

Abstract: PURPOSE:To increase greatly the reliability of a system, by using a changeable storage means in each processor and fetching either one of the systems by the on-/off-mode of the storage means. CONSTITUTION:A storage means which can be set and reset by a program or another means is set in each memory expander 4 or CPU3, and the transmission of either one of both reading data to the CPU is decided by the on-/off-mode of this storage means when these two reading data are normal. In such way, some group of plural CPUs 3 uses the data of a shared memory M1 with priority, and the rest groups of CPU3 use the data of a shared memory M2 with priority respectively. As a result, the breakdown of all CPUs can be avoided although the errors occur frequently at a single system sharing memory for the data to which the detection of error is impossible.

Abstract: A method of controlling processes with a central controller consisting of several processors with stored programs enables simple operation with individual procedures. A main processor is not required and access to a central store (Zs) via common data channels is minimised. The operating data of the processors, which generate peripheral unit access demands, are placed in common central or distributed memories associated with the processes and/or the peripheral devices. All processors (P1-Pn) can deal with all types of processes in an identical manner. The processes are distributed to processors as they arise by an allocation unit (AZ) programmed to produce uniformity of loading programs, temporary process data, and intermediate results are held in individual program and operating memories (PASI-PASA). Each processor indicates when it is free to be selected.