Abstract: A plurality of processors and memory modules arranged in a hierarchy are connected in a network such that memory sharing can occur during processor operations, and control means are provided so as to regulate protected usage of specific areas of the memory modules. A Global Memory Module (GMM) and a system hierarchy of processors is described which provides access to a plurality of addressable memory storage units. A multiple number of processors or computer systems are connected to one or more Global Memory Modules whereby memory resources may be shared by multiple processor systems and where control and communications are provided between the processors through the Global Memory Modules. The Global Memory Module may be organized into a hierarchy of Global Memory Module systems whereby processors attached to "lower level" GMM systems may access memory in "higher level" GMM systems. Means are provided whereby a processor in one GMM system may send commands and messages to a processor in another GMM system. Means are provided by which one processor can address another specific processor in the system network or whereby one processor can address an "available" processor in a system designated under a system name, and the network will choose the processor which is "idle" or, if there is no idle processor available, will then choose a processor which is "not engaged", that is to say, a processor which when it finishes its currently scheduled activities, will then be available for processing of a received command and message.

Abstract: A network is described wherein a plurality of processors are connected in a hierarchy of levels with provision for communication between the various processors. A Global Memory Module (GMM) and a system hierarchy of processors is described which provides access to a plurality of addressable memory storage units. A multiple number of processors or computer systems are connected to one or more Global Memory Modules whereby memory resources may be shared by multiple processor systems and where control and communications are provided between the processors through the Global Memory Modules. The Global Memory Module may be organized into a hierarchy of Global Memory Module systems whereby processors attached to "lower level" GMM systems may access memory in "higher level" GMM systems. Means are provided whereby a processor in one GMM system may send commands and messages to a processor in another GMM system. Means are provided by which one processor can address another specific processor in the system network or whereby one processor can address an "available" processor in a system designated under a system name, and the network will choose the processor which is "idle" or, if there is no idle processor available, will then choose a processor which is "not engaged", that is to say, a processor which when it finishes its currently scheduled activities, will then be available for processing of a received command and message.

Abstract: A Global Memory Module (GMM) and a system hierarchy of processors is described which provides access to a plurality of addressable memory storage units. A multiple number of processors or computer systems are connected to one or more Global Memory Modules whereby memory resources may be shared by multiple processor systems and where control and communications are provided between the processors through the Global Memory Modules. The Global Memory Module may be organized into a hierarchy of Global Memory Module systems whereby processors attached to "lower level" GMM systems may access memory in "higher level" GMM systems. Means are provided whereby a processor in one GMM system may send commands and messages to a processor in another GMM system. Means are provided by which one processor can address another specific processor in the system network or whereby one processor can address an "available" processor in a system designated under a system name, and the network will choose the processor which is "idle" or, if there is no idle processor available, will then choose a processor which is "not engaged", that is to say, a processor which when it finishes its currently scheduled activities, will then be available for processing of a received command and message. The Global Memory Module has input ports for connection to a local individual processor or to another Global Memory Module. The GMM has (1) a Global Memory Control Section for handling requests for access to memory and (2) a Global System Control Section for control of messages between a processor and its GMM.

Abstract: : Cm* is an extensible, multiprocessor computer, system with a hierarchical structure. A 10 processor pilot system, has been in operation for a year. The hardware structure will support on the order of 10,000 processors. A major overall design objective is to efficiently support close cooperation between large numbers of concurrently executing processes. An important component of multiprocessor systems is the switching structure which allows processors to access shared memory. The effective, maximum size (in number of processors) of multiprocessors described in the literature is limited. This limitation comes either through saturation of the access path to shared memory, or through the rapid growth of switch cost. The hierarchical switching structure of Cm* offers, in principle, indefinite extensibility of processing power, memory capacity and communication bandwidth. The cost of the interconnection structure grows approximately linearly with system size. Effective use of the structure depends on suitable decompositions of applications.

Abstract: A multiprocessor system is described which allows for the sharing of memories between the individual processors having synchronous memory interfaces. Three processing units are shown by way of example, each processor having its own local, associated memory. Two of the processing units can each access its own memory but not any other memory. The third processing unit can access its own memory as well as the memories associated with the other two processing units. An engine interface adapter interconnects the I/O busses of the processing units. The functions performed by the engine interface adapter can be divided into two principal groups. The first group of functions permits communication between the processors via their I/O busses. The second group of functions permits the aforedescribed sharing of the memory units between the processing units.

Abstract: An integrating processor element containing a data processor that provides a computer with those functions normally associated with the Central Processor Unit (CPU) but which possesses architectural features to prevent compromise (i.e., unauthorized dissemination) of data in a multi-level secure environment. The data processor executes instructions from an internal instruction memory which cannot be altered by the data processor and cannot be accessed by the I/O processor (i.e., I/O controller). The instruction memory is segmented providing a separate segment for each discrete level of secure data to be processed. Each computer program is stored in the segment corresponding to the highest level of security of the data it will use. A second memory, called the hand-off memory, is a read/write memory accessible by the I/O processor as well as the data processor. The hand-off memory is also segmented by security level. A computer program may only write in the hand-off memory in the segment corresponding to the same security level as the segment in the instruction memory in which it is stored. A computer program may read, however, from any segment corresponding to the same or a lower security level. The data processor contains a security register which provides the hardware assurance that a computer program can access only permitted data. A memory address translator within the data processor is provided to permit relocation of segments within the hand-off memory without corresponding changes to any computer program. This feature enables generation of computer programs having lower classifications than the data upon which they operate.

Abstract: General models of multiprocessor systems in which processors are functionally dedicated are described In these models, processors are divided into different types A task can be assigned only to a processor of certain types Clearly, the model of multiprocessor systems with identical processors is a special case of our models These models also include the job shop problem in which there is exactly one processor of each type Worst case performance bounds of priority-driven schedules are obtained

Abstract: The memory hierarchy is usually the largest identifiable part of a computer system and making effective use of it is critical to the operation and use of the system. We consider the levels of such a memory hierarchy and describe the state of the art and likely directions for both research and development. Algorithmic and logical features of the hierarchy not directly associated with specific components are also discussed. Among the problems we believe to be the most significant are the following: (a) evaluate the effectiveness of gap filler technology as a level of storage between main memory and disk, and if it proves to be effective, determine how/where it should be used, (b) develop algorithms for the use of mass storage in a large comguter system and (c) determine how cache memories should be implemented in very large, fast multiprocessor systems.

Abstract: This paper discusses the design of interconnection modules for a multiprocessor system which consists of many small and functionally specialized processors. It is proposed that the information, i.e. programs, data etc., used in the system should be divided into three categories; private information, command data and shared data, according to the analysis of software simulation results. Private information is stored in a memory provided exclusively for each processor. Command data is transferred directly between processors to initiate a function in other processors. Shared data is stored in a memory shared by several processors. For command data and shared data, two different connection modules are provided; the interprocessor connection module using common bus technique, and the processor-memory connection module using crossbar switch technique. The effects of information partitioning on the performance and cost of the system are analyzed. It is verified that the interprocessor connection module technique is preferable than a few possible alternatives through the design analysis and the implementation of a pilot model system.

Abstract: The performance of various memory configurations for parallel-pipelined computer which execute multiple instruction streams on multiple data streams is investigated.For a parallel-pipelined processor of order (s,p), which consists of p parallel processors each of which is a pipelined processor with s degrees of multiprogramming, there can be up to s p memory requests in each instruction cycle. The memory, which consists of N(=2n) identical memory modules, is organized such that there are l(=2i) lines and m(=2n-i) modules per line, where each module is characterized by the address cycle (address hold time)and memory cycle of a and c time units respectively.The performance which is affected by the memory interference problem is evaluated as a function of the memory configuration, (l, m), the module characteristics (a, c) and the processor order (s, p). Design considerations are discussed and an example given to illustrate possible design options.