Abstract: The object of this paper is to bring together several models of interleaved or parallel memory systems and to expose some of the underlying assumptions about the address streams in each model. We derive the performance for each model, either analytically or by simulation, and discuss why it yields better or worse performance than other models (e.g., because of dependencies in the address stream or hardware queues, etc.). We also show that the performance of a properly designed system can be a linear rather than a square root function of the number of memories and processors.

Abstract: A distributed function processing system utilizing a conventional microprocessor operated as a text processor in combination with a plurality of other autonomous processing devices arranged to operate in a coherent processing system. One of the autonomous processors which is a memory control processor serves to periodically overlay a random access accelerator memory with the contents of a main memory system and concurrently resolves conflicts among various other autonomous memory service requests. This processor, therefore, accommodates the data rates of the main memory. The other processor is a display processor which generates signals to a video display system to provide a visual interface to the user and is therefore tied to the video rate. Accordingly, the processing burden is distributed within processors entailing differing rates operating autonomously. The memory control processor resolves and accommodates all of the memory service requests in the system and also performs control operations to support high speed I/O devices. Logic is provided to handle the other interrupts. Also, there is page mapping for context switching of a reference page and repeating logic for decoupling this processor from the other processors. This arrangement allows convenient expansion into plural work stations each sharing a common memory.

Abstract: e of 35 dynamic memory allocation algorithms when used to service simulation programs as represented by 18 test cases. Algorithm performance was measured in terms of processing time, memory usage, and external memory fragmentation. Algorithms maintaining separate free space lists for each size of memory block used tended to perform quite well compared with other algorithms. Simple algorithms operating on memory ordered lists (without any free list) performed surprisingly well. Algorithms employing power-of-two block sizes had favorable processing requirements but generally unfavorable memory usage. Algorithms employing LIFO, FIFO, or memory ordered free lists generally performed poorly compared with others.

Abstract: A network of two or more microprogrammed digital processors is provided which permits operation of the individual processors independently or as linked processors for transferring real time control information at the micro level to establish microprogram control which is supplied from the processor that is processing the data determining the control sequence, resulting in dynamic master/slave relationships, with high performance, by eliminating the need to transfer data used to influence microprogramming sequencing. Next control memory address source designators within each processor, selectively enable microprogram control memory data sources of either processor when the control memory address busses of each processor are linked together. Upon unlinking of the address busses, each next control memory address source designator selectively enables a source only within its own processor, such as a branch address latch source, operation code mapping memory source, and a microsequencer source. Permanently linked processors provide a single processor network for achieving increased performance for multiple precision computations.

Abstract: ture of shared memory in a multiprocessor computer system is examined with particular attention to noninterleaved memory. Alternative memory organizations are compared and it is shown that a home memory organization, in which each processor is associated with one or more memories in which its address space is concentrated, is quite effective in reducing memory interference. Home memory organization is shown to be particularly suited to certain specialized computational problems as well as to possess advantages in terms of interference and reliability for general purpose computation. Results for interleaved memory are drawn from previous work and are used for comparison. Trace-driven simulations are used to verify the conclusions of the analysis.

Abstract: A parallel processor having a large number of elementary processors connected in parallel to an address bus and a control bus. Each elementary processor contains a memory and control and processing circuits to perform calculations on bits addressed in the memory and bits coming either from this memory or from a peripheral unit. Each elementary processor further contains a small capacity fast memory and the control and processing circuit contains a single storage flip-flop able to perform calculations in series on the bits extracted from the memories and/or coming from the peripheral unit. All the fast memories are parallel connected.

Abstract: A shared random-access memory resource is described which is used within real-time data acquisition and control systems with multiprocessor and multibus organizations. Hardware and software aspects are discussed in a specific example where interconnections are done via a UNIBUS. The general applicability of the approach is also discussed.

Abstract: Analytic and simulation models of memory interference have been reported in the literature. These models provide tools for analyzing various system architecture alternatives. Some of the design parameters are processor speed, memory speed, number of processors, number of memories, use of cache memories, high-order versus low-order interleaving, and memory allocation. This correspondence applies existing analytic and simulation models to the multiprocessor design space and presents guidelines for the multiprocessor system architect. Preferred design alternatives and tradeoffs are outlined.

Abstract: This paper reports results of a study to determine and compare the effectiveness of various techniques aimed at reducing memory interference in multiprocessor multi memory systems. A simulation model of a multiprocessor, driven by address traces, is used for evaluation purposes. Two approaches to interference reduction are considered, being the reduction of overlapping memory requirements through various memory allocation methods, and the use of local memory to reduce the request rate to shared memory. Both private and cache memory are considered for this purpose.

Abstract: The performances of two types of multiprocessor systems with cache memories dedicated to each processor are analyzed. It is demonstrated that by appropriate cache system design, adequate memory system speed can be achieved to keep the processors busy. A write through algorithm is used for each cache to minimize directory searching and several main memory modules are used to provide interleaved write. In large memories a cost performance analysis shows that with an increase in per bit costs of 5 to 20 percent, the memory throughput can be enhanced by a factor of 10 and by a factor of 3 or more over simple interleaving of the modules for random memory requests. Experimental evidence indicates smaller cache memories are required for dedicated processors than for standard processors. All memories and buses can be of modest speed.

Abstract: The design of a state-of-the-art, high-performance data processor is presented. A general description of the S-1 multiprocessor architecture and an overview of the organization of a specific S-1 multiprocessor configuration are given first. Then processor architecture is described in detail, including caches, virtual memory, memory access modes, status, I/O, and instruction set definition. The S-1 design system (SCALD) used to design and implement both single- and multiprocessor configuration is then discussed. Finally, the detailed design and hardware implementation of the first prototype S-1 processor are presented. 388 figures. (RWR)

Abstract: Memory management, database management, and message processing have in the past been defined in a relatively narrow way. With memory management the problem was to obtain cost effective use of real memory. Given a multiprogrammed environment, virtual memory systems allowed more effective use of expensive real memory. Memory management has become even more important with the development of very large and complex memory hierarchies. Database management systems were developed to allow the more effective use, sharing, and control of data resources - objectives which operating systems had previously provided for hardware resources. The driving force behind message processing has been the increased use of data communications and computer networks. This paper will consider the basis of the overlap in these areas, their common data management functions. Data management, as defined in this paper, includes the locating, routing, moving, and translating of data resources and the locating, reserving, and releasing of physical resources, i.e., primary and secondary storage.The analysis performed in this paper is essential because of trends in computer architecture discussed below. Early hardware was designed for general purpose environments with software used to tailor it to specific applications. However, according to Gagliardi9 future systems will consist of a set of subsystems, including a storage subsystem at the core surrounded by computational, spooling, and communications subsystems. The computational subsystem is the traditional “number cruncher” part of the system. The spooling subsystem provides the I/O interface between the system and the outside world. The communications subsystem links the various subsystems together and provides an interface to the rest of the network if the system is part of a larger distributed system. The storage subsystem consists of all the system's storage resources and their control processes. It controls all levels of the system memory and storage hierarchy. The storage subsystem controls the allocation of the physical storage resources and the movement of the data resources through the system. Depending on how these resources are used, they may be non-conserved or conserved, and if conserved, either serially reusable or sharable. Physical and data resources may be located, and if necessary reserved, independently or jointly.

Abstract: : The object of this research is to develop a flexible semiconductor memory organization for parallel-pipelined processors and investigate the effect of memory interference on the system performance for a variety of module characteristics, processor orders and memory configurations.

Abstract: A comparison of priority queues on four different types of computer memories are made by ring a model to determine the total time to do comparable tasks. The four types of memories compared are random access (RAM), associate (AM), hybrid consisting of an associate memory and a random access memory (AM/RAM), and the hybrid memory with an auxiliary memory having the

Abstract: The performance of one arrangement of the multiprocessor computer with local memories is established. Namely the following influences are shown: the processing time between two accesses to main memory, the time for page transfer, and the time needed for working up each such interrupt on the degree of usage of the processors and on the throughput of the system.

Abstract: This paper describes the architecture of a new large multi-processor computer system being built at Carnegie-Mellon University. The system allows close cooperation between large numbers of inexpensive processors. All processors share access to a single virtual memory address space. There are no arbitrary limits on the number of processors, amount of memory or communication bandwidth in the system. Considerable support is provided for low level operating system primitives and inter-process communication.

Abstract: : This paper describes the architecture of a new large multiprocessor computer system being built at Carnegie-Mellon University. The system allows close cooperation between large numbers of inexpensive processors. All processors share access to a single virtual memory address space. There are no arbitrary limits on the number of processors, amount of memory or communication bandwidth in the system. Considerable support is provided for low level operating system primitives and inter-process communication. (Author)