Abstract: A multiprocessor microcomputer system having two or more substantially independent processors each of which has its own bus-type interconnection structure, and a shared memory accessible by any of the processors without interferring with the proper operation of the other processors. Controlled access to the memory by connecting the memory to the processor requesting access when only one such request is present and to the last processor to have received access when more than one request is received simultaneously allows autosynchronous operation, automatic selection of priority and high speed of operation.

Abstract: A multidimensional parallel access computer memory system is provided to facilitate high speed parallel access of data from a multi-bank computer memory. The system is particularly adapted to matrix calculations whereby matrix elements along linear matrix vectors are nonconflictingly stored in a plurality of independent memories and are associated in parallel with a plurality of independent processors for high speed matrix manipulations. An alignment network interposing the plurality of memories and the plurality of processors responds to the generation of memory and address tags to associate a particular matrix element stored in a particular memory address with a particular processor for processing.

Abstract: Virtual memory is one of the major concepts that has evolved in computer architecture over the last decade. It has had a great impact on the design of new computer systems since it was first introduced by the designers of the Atlas computer in 1962. A virtual memory is usually divided into blocks of contiguous locations to allow an efficient mapping of the logical addresses into the physical address space. In this paper, we are concerned with paging systems, that is, systems for which the blocks of contiguous locations are of equal size. The memory system consists of two levels: main memory and auxiliary memory. The occurrence of a reference to a page that is currently not in main memory is called a page fault. A page fault results in the interruption of the program and the transfer of the referenced page from auxiliary to main memory.

Abstract: The analysis in this paper shows a multiprocessor like C.mmp to have a factor of three to four cost/performance advantage over uniprocessor systems such as the PDP-10 when implementations using similar technologies are considered. This comparison is shown to be very sensitive to memory prices and considerable attention is given to normalizing memory costs between C.mmp and the PDP-10. An important part of this analysis is a comparison of the PDP-10 architecture with the PDP-11 architecture (i.e. the architecture of the processors of C.mmp). When the limited address space of the PDP-11 is not a problem, we see that to a close approximation it takes the same number of PDP-11 instructions (average length 25 bits) as PDP-10 instructions (length 36 bits) to represent a program. While the comparison in this paper explicitly considers multiprocessor degradation factors such as memory interference, it does not address the problem of writing software systems capable of taking full advantage of the multiprocessor structures. The comparisons in this paper are primarily ofcused on comparing the hardware structures of uniprocessors and multiprocessors. Work is now in progress at CMU that is attempting to evaluate the effectiveness of both individual multiprocessor structures application programs and multiprogrammed systems operating on C.mmp.

Abstract: In a multiprocessor system having a plurality of processors, each of identical construction, each processor is internally equipped with a fixed address supply source which generates a non-unique fixed address for accessing a common memory unit over commonly connected bus lines, and a sequential state indicate signal generator for generating a logic "1" or "0" synchronizing signal when a special condition (for example, interrupt) occurs with respect to the processor. A shared memory access control system for a multiprocessor system, as above described, includes circuitry, external to and associated with at least each processor except for one processor, responsive to the synchronizing signal from its respective processor for modifying the non-unique fixed address from the respective processor so that, as a result, each processor is able to address the common memory over the commonly connected bus lines with a unique fixed address.

Abstract: The memory structure of a computer refers to those hardware elements that store the data elements and the related information during program execution. It has a great impact upon the usage and the programming of the computer. Since the advent of commercial electronic digital computers, the memory has made great hardware advances in speed, capacity, size, cost and reliability. It has also made great organizational changes.This paper reviews the memory structure of typical computers from the viewpoint of the software need. It emphasizes the structural advances in satisfying the software need of various types of data elements and data structures. It presents observations of the evolutionary nature of the memory structure development toward the high-level language architecture.

Abstract: Continuing advances in semiconductor technology now makes practical the construction of multi-micro-processor systems with tens to hundreds of processors. We are currently involved in the design and construction of a multi-micro-processor system to experimentally investigate the problems of building and programming systems with a large number of processors. The LSI-11 microcomputer is the basic “computer module” that provides processing power and primary memory. The interconnection scheme between the computer modules allows the processors to cooperate in a true multiprocessor fashion: they can share and efficiently access all of primary memory. A number of working groups are now investigating the central problems facing the design and successful application of reliable multi-micro-processor systems and these problems will also be discussed.

Abstract: This paper presents the results of an effort to determine the performance, operational characteristics, hardware and software requirements, and the potential applications base for a symmetric system of closely coupled multiprocessors. Based on experience described herein, multiprocessing provides an effective way to increase the range of system performance with a single CPU product line, thereby serving a wider class of applications and market areas and providing explicit growth channels for applications whose computing requirements grow in time.A prototype system has been built using PDP-11/40 processors, multiported memories, and UNIBUS windows, for the purpose of determining its performance and operational characteristics. The RSX-11M real time operating system has been modified to support multiprocessing on this configuration. Theoretical analysis has provided a mathematical expression for system throughput as a function of the number of processors, memory banks, and memory utilization factors. Performance measurements have been related to theoretical analysis so that analytic means can predict the performance of configurations beyond the scope of the prototype hardware.For certain applications, the system cost-performance ratio is improved. The cost effectiveness of multiprocessing is contingent upon low processor/bus utilization of memory, or a high degree of parallelism in the memory system, such as interleaving or banking. Furthermore, realization of the potential afforded by multiprocessing hardware can only be attained in properly structured multiprogrammed operating systems.

Abstract: This paper describes a specialized parallel computer architecture that is proposed for high-speed searching of large text data bases. The proposed machine architecture is a parallel array of independent processors connected to a common bus. Each processor consists of a microprocessor, a high-speed block-access memory for storage of a part of the data base, read-only memory for control software, and random-access memory for storage of programs and working storage. The processors are connected by a common high-speed bus that is used for communication of data, programs, commands and results. The benefits claimed for this architecture are design simplicity, high speed for suitable applications, ease of software development, reliability and reasonable cost. This machine architecture is under consideration as a means for providing high-speed text searching capabilities.

Abstract: This paper analyzes the memory interference caused by several processors simultaneously using several memory modules. Exact results are computed for a simple model of such a system. The limiting value is derived for the relative degree of memory interference as the system size increases. The model of the limiting behavior of the system yields approximate results for the simple model and also suggests that the results are valid for a much larger class of models, including those more nearly like real systems than the simple model. The assumptions and results of the simple model are tested against some measurements of program behavior and simulations of systems using memory references from real programs. The model results provide a good indication of the performance that should be expected from real systems of this type.