Showing papers on "Distributed memory published in 1973"
TL;DR: A cache-based computer system employs a fast, small memory interposed between the usual processor and main memory that provides a smaller ratio of memory access times, and holds the processor idle while blocks of data are being transferred from main memory to cache rather than switching to another task.
Abstract: A cache-based computer system employs a fast, small memory -the " cache" - interposed between the usual processor and main memory. At any given time the cache contains as much as possible the instructions and data the processor needs; as new information is needed it is brought from main memory to cache, displacing old information. The processor tends to operate with a memory of cache speed but with main memory cost-per-bit. This configuration has analogies with other systems employing memory hierarchies, such as "paging" or "virtual memory" systems. In contrast with these latter, a cache is managed by hardware algorithms, deals with smaller blocks of data (32 bytes, for example, rather than 4096), provides a smaller ratio of memory access times (5:1 rather than 1000: 1), and, because of the last factor, holds the processor idle while blocks of data are being transferred from main memory to cache rather than switching to another task. These are important differences, and may suffice to make the cache-based system cost effective in many situations where paging is not.
92 citations
Patent•
1 Oct 1973
TL;DR: In this article, an improved data processor architecture with integrated circuit (IC) memories is presented, where memory refresh is provided in response to instruction execution, synchronized with computer control signals to minimize contension or conflicts with computer operations.
Abstract: An improved data processor architecture is provided having integrated circuit (IC) memories. Provision is made for dynamic memories with a memory refresh arrangement. Memory refresh is provided in response to instruction execution, synchronized with computer control signals to minimize contension or conflicts with computer operations and to share control circuitry.
19 citations
TL;DR: This paper investigates some of the problems that arise when several microprocessors share a common control memory and a common main memory and tests a set of Digital Scientific Meta 4's operating in IBM 1130 emulation mode.
Abstract: This paper investigates some of the problems that arise when several microprocessors share a common control memory and a common main memory. The performance with respect to both control and main memory accessing conflicts is measured for several system configurations by means of a simulation program. The program tests a set of Digital Scientific Meta 4's operating in IBM 1130 emulation mode.
9 citations
1 Apr 1973
TL;DR: Various analytic techniques for studying the extent of memory interference in a multiprocessor system with a crosspoint switch for processor-memory communication are surveyed, including discrete and continuous time Markov chain models and some approximate analytic methods, viz. diffusion approximation and Strecker's approximation.
Abstract: : The paper surveys various analytic techniques for studying the extent of memory interference in a multiprocessor system with a crosspoint switch for processor-memory communication. Processor behavior is simplified to an ordered sequence of a memory request followed by a certain amount of processing time. The system is assumed to be bus bound; in other words, by the time the processor-memory bus completes servicing a processor's request the processor is ready to initiate another request and the memory module is ready to accept another request. The techniques discussed include discrete and continuous time Markov chain models, and some approximate analytic methods, viz. diffusion approximation and Strecker's approximation. The results are compared with a simulation model, in which the processing time has an exponential distribution and the memory cycle time is constant. (Author)
3 citations