Abstract: A small size digital computer system is designed so that a hardware memory violation protect subsystem may be added to the computer system as a hardware option. The memory protect subsystem includes hardware which may operate in parallel with the digital computer system memory subsystem and which monitors each attempt to alter data within the memory subsystem. Any attempt to alter data within a protected region may be defeated. Following such an attempt, program execution is interrupted and program control is transferred to the computer system executive software. The computer system is also designed so that it may either modify or prevent the execution of certain instructions at times when the memory protect subsystem is in operation so as to defeat all attempts on the part of any software entity to destroy the integrity of the operating system.

Abstract: Dynamic memories are commonly constructed as circulating shift registers, and thus have access times that are proportional to the size of memory. When each word in a dynamic memory is connected to r words, r ? 2, access time can be proportional to the base r logarithm of the size of memory. A memory that achieves minimum access time for r = 2 is described. The memory can also be operated in an efficient binary search mode. Slight variations of the interconnection patterns lead to a memory that is well suited for FFT and certain matrix computations.

Abstract: A programmable input-output processor has been provided for use with multiple channel data acquisition systems such as the CAMAC dataway, a standardized digital system that is capable of handling vast amounts of digital data. The processor acts as a branch driver which provides multiple channel direct memory access to a host computer via a single memory access interface. Command lists in computer memory select microprogrammed sequences, stored in a fast-access control memory, which transfer data between CAMAC devices and lists in computer memory.

Abstract: An access unit for a shared memory for use in a microprogrammable processor is provided utilizing a multiplexing scheme. Two functionally different inputs, one for data, the other for microinstructions are exclusively gated to memory in synchronization with microprogram control timing cycles to permit accessing the memory at separate times via a single channel.