Distributed active transformer

Abstract: A novel on-chip impedance matching and power-combining method, the distributed active transformer is presented. It combines several low-voltage push-pull amplifiers efficiently with their outputs in series to produce a larger output power while maintaining a 50-/spl Omega/ match. It also uses virtual ac grounds and magnetic couplings extensively to eliminate the need for any off-chip component, such as tuned bonding wires or external inductors. Furthermore, it desensitizes the operation of the amplifier to the inductance of bonding wires making the design more reproducible. To demonstrate the feasibility of this concept, a 2.4-GHz 2-W 2-V truly fully integrated power amplifier with 50-/spl Omega/ input and output matching has been fabricated using 0.35-/spl mu/m CMOS transistors. It achieves a power added efficiency (PAE) of 41 % at this power level. It can also produce 450 mW using a 1-V supply. Harmonic suppression is 64 dBc or better. This new topology makes possible a truly fully integrated watt-level gigahertz range low-voltage CMOS power amplifier for the first time.

Abstract: In this paper, a distributed active transformer for the operation in the millimeter-wave frequency range is presented. The transformer utilizes stacked coupled wires as opposed to slab inductors to achieve a high coupling factor of kf=0.8 at 60 GHz. Scalable and compact equivalent-circuit models are used for the transformer design without the need for full-wave electromagnetic simulations. To demonstrate the feasibility of the millimeter-wave transformer, a 200-mW (23 dBm) 60-GHz power amplifier has been implemented in a standard 130-nm SiGe process technology, which, to date, is the highest reported output power in an SiGe process technology at millimeter-wave frequencies. The size of the output transformer is only 160times160 mum2 and demonstrates the feasibility of efficient power combining and impedance transformation at millimeter-wave frequencies. The two-stage amplifier has 13 dB of compressed gain and achieves a power-added efficiency of 6.4% while combining the power of eight cascode amplifiers into a differential 100-Omega load. The amplifier supply voltage is 4 V with a quiescent current consumption of 300 mA

Abstract: There is a growing demand for the implementation of the RF power amplifier (PA) in CMOS technologies, due to its cost and integration benefits. Most of the already reported CMOS PAs do not have sufficient output power nor linearity to cope with the long term evolution (LTE) requirements. In this paper, the linearity requirements for power amplifiers targeting LTE-applications are investigated. Based on this system level analysis, a single-chip fully integrated CMOS power amplifier with sufficient power and linearity for emerging E-UTRA/LTE-applications is designed. This 90-nm LTE-band VIII CMOS linear power amplifier uses a distributed active transformer (DAT) as power combiner and delivers an output power up to 29.4 dBm with 25.8% power-added efficiency (PAE) and has 28-dB small-signal gain. The choice of optimal biasing ensures a very flat gain and small AM-PM distortion up to high output power. While applying an uplink LTE signal, the PA produces 25 dBm of average output power with 15% PAE while obeying the stringent EVM-specifications.

Abstract: In this paper, a fully integrated 0.13-mum CMOS RF power amplifier for Bluetooth is presented. Four differential amplifiers are placed on a single chip and their outputs are combined with an on-chip LC balun structure. This technique allows to have a low impedance transformation ratio for each individual amplifier, and thus a lower power loss. The amplifier achieves a measured output power of 23 dBm at a supply voltage of 1.5 V and a drain efficiency of 35% and a global efficiency of 29%. The parallel amplification topology allows to efficiently control the output power which results in an efficiency improvement when the output power is reduced.