Topic
Direct mode
About: Direct mode is a research topic. Over the lifetime, 285 publications have been published within this topic receiving 3834 citations.
Papers published on a yearly basis
Papers
TL;DR: In this article, a Boltzmann machine (BM) with symmetric connections is designed to implement a given truth table, and it can be interconnected in a partially directed manner to implement large operations such as 32-bit addition.
Abstract: Conventional logic and memory devices are built out of deterministic units such as transistors, or magnets with energy barriers in excess of 40-60 kT. We show that stochastic units, p-bits, can be interconnected to create robust correlations that implement Boolean functions with impressive accuracy, comparable to standard circuits. Also they are invertible, a unique property that is absent in digital circuits. When operated in the direct mode, the input is clamped, and the network provides the correct output. In the inverted mode, the output is clamped, and the network fluctuates among possible inputs consistent with that output. We present an implementation of an invertible gate to bring out the key role of a three-terminal building block to enable the construction of correlated p-bit networks. The results for this implementation agree well with those from a universal model, showing that p-bits need not be magnet-based: any three-terminal tunable random bit generator should be suitable. We present an algorithm for designing a Boltzmann machine (BM) with symmetric connections that implements a given truth table. We then show how BM Full Adders can be interconnected in a partially directed manner to implement large operations such as 32-bit addition. Hundreds of p-bits get precisely correlated such that the correct answer out of 2^33 possibilities can be extracted by looking at the mode of a number of time samples. With perfect directivity a small number of samples is enough, while for less directed connections more samples are needed, but even in the former case invertibility is largely preserved. This combination of accuracy and invertibility is enabled by the hybrid design that uses bidirectional units to construct circuits with partially directed connections. We establish this result with examples including a 4-bit multiplier which in inverted mode functions as a factorizer.
292 citations
Patent•
27 Feb 1998
TL;DR: In this article, a system for coding of digital video images such as bi-directionally predicted video object planes (B-VOPs), in particular, where the B-VOPS and/or a reference image used to code the BVOP is interlaced coded, is presented.
Abstract: A system for coding of digital video images such as bi-directionally predicted video object planes (B-VOPs), in particular, where the B-VOP and/or a reference image used to code the B-VOP is interlaced coded. For a B-VOP macroblock which is co-sited with a field predicted macroblock of a future anchor picture, direct mode prediction is made by calculating four field motion vectors, then generating the prediction macroblock. The four field motion vectors and their reference fields are determined from (1) an offset term of the current macroblock's coding vector, (2) the two future anchor picture field motion vectors, (3) the reference field used by the two field motion vectors of the co-sited future anchor macroblock, and (4) the temporal spacing, in field periods, between the current B-VOP fields and the anchor fields. Additionally, a coding mode decision process for the current MB selects a forward, backward, or average field coding mode according to a minimum sum of absolute differences (SAD) error which is obtained over the top and bottom fields of the current MB.
226 citations
Patent•
30 Jun 2007TL;DR: In this article, video decoding innovations for multithreading implementations and graphics processor unit (GPU) implementations are described, where a decoder uses innovations in the areas of layered data structures, picture extent discovery, a picture command queue, and/or task scheduling for multi-reading.
Abstract: Video decoding innovations for multithreading implementations and graphics processor unit (“GPU”) implementations are described. For example, for multithreaded decoding, a decoder uses innovations in the areas of layered data structures, picture extent discovery, a picture command queue, and/or task scheduling for multithreading. Or, for a GPU implementation, a decoder uses innovations in the areas of inverse transforms, inverse quantization, fractional interpolation, intra prediction using waves, loop filtering using waves, memory usage and/or performance-adaptive loop filtering. Innovations are also described in the areas of error handling and recovery, determination of neighbor availability for operations such as context modeling and intra prediction, CABAC decoding, computation of collocated information for direct mode macroblocks in B slices, reduction of memory consumption, implementation of trick play modes, and picture dropping for quality adjustment.
171 citations
Patent•
30 Jun 2007TL;DR: In this paper, video decoding innovations for multithreading implementations and graphics processor unit (GPU) implementations are described, where a decoder uses innovations in the areas of layered data structures, picture extent discovery, a picture command queue, and/or task scheduling for multi-reading.
Abstract: Video decoding innovations for multithreading implementations and graphics processor unit (“GPU”) implementations are described. For example, for multithreaded decoding, a decoder uses innovations in the areas of layered data structures, picture extent discovery, a picture command queue, and/or task scheduling for multithreading. Or, for a GPU implementation, a decoder uses innovations in the areas of inverse transforms, inverse quantization, fractional interpolation, intra prediction using waves, loop filtering using waves, memory usage and/or performance-adaptive loop filtering. Innovations are also described in the areas of error handling and recovery, determination of neighbor availability for operations such as context modeling and intra prediction, CABAC decoding, computation of collocated information for direct mode macroblocks in B slices, reduction of memory consumption, implementation of trick play modes, and picture dropping for quality adjustment.
159 citations
Patent•
30 Jun 2007TL;DR: In this article, video decoding innovations for multithreading implementations and graphics processor unit (GPU) implementations are described, where a decoder uses innovations in the areas of layered data structures, picture extent discovery, a picture command queue, and/or task scheduling for multi-reading.
Abstract: Video decoding innovations for multithreading implementations and graphics processor unit (“GPU”) implementations are described. For example, for multithreaded decoding, a decoder uses innovations in the areas of layered data structures, picture extent discovery, a picture command queue, and/or task scheduling for multithreading. Or, for a GPU implementation, a decoder uses innovations in the areas of inverse transforms, inverse quantization, fractional interpolation, intra prediction using waves, loop filtering using waves, memory usage and/or performance-adaptive loop filtering. Innovations are also described in the areas of error handling and recovery, determination of neighbor availability for operations such as context modeling and intra prediction, CABAC decoding, computation of collocated information for direct mode macroblocks in B slices, reduction of memory consumption, implementation of trick play modes, and picture dropping for quality adjustment.
157 citations
Related Topics (5)
Performance Metrics
| Year | Papers |
|---|---|
| 2021 | 5 |
| 2020 | 9 |
| 2019 | 2 |
| 2018 | 6 |
| 2017 | 13 |
| 2016 | 9 |