TL;DR: In this article, a time notarization scheme based on a secure, microprocessor-based hardware platform which performs public key signature operations with a minimum of intervention by third parties is presented.
Abstract: A time notarization apparatus and method is disclosed which uses a secure, microprocessor based hardware platform which performs public kay cryptographic operations to obtain trusted time stamping with a minimum of intervention by third parties. The hardware platform is encapsulated in a secure fashion so that the device's timestamping mechanism may not be readily tampered with or altered. The hardware platform includes at least one digital clock (4) and a stable, secure storage device (8) to record the private half of a public/private key pair. Coupled to both the digital clock (4) and the storage device (8) is a data processing device (6) which performs public key signature operations in a secure and tamper-proof manner. Only the processing device (6) has access to the secure storage device (8) and its associated private key. The hardware platform also includes input/output means which receives a digital message which is to be digitally signed and timestamped and which outputs the resulting timestamped signature generated by the device. The hadware platform also includes a power source (12), (e.g., an on-board battery) to ensure the accuracy of the device's digital clock (4) and the security of storage data prior to installation or in case of a power failure.
TL;DR: In this article, a system for programming the automatic operation of a video recorder over an extended time period uses an associated television receiver as a display device for alphanumeric messages to the operator to provide a self-explanatory, interactive programming routine.
Abstract: A system for programming the automatic operation of a video recorder over an extended time period uses an associated television receiver as a display device for alphanumeric messages to the operator to provide a self-explanatory, interactive programming routine. The video recorder system includes a digital memory, a real time digital clock, and an alphanumeric character generator, all connected to a central digital controller. A keypad allows the operator to initiate a programming routine in which previously stored programming messages are called up from memory and generated on the TV receiver's display tube using the character generator. The operator's responses entered via the keypad are stored in the memory and are called up at future times to generate control signals for the video recorder. The video recorder system further includes a memory storing digital data representing a schedule of programming available for a future period. The video system permits this schedule to be recalled and displayed on the TV receiver for review by the user.
TL;DR: An improved rear view mirror which may contain any of a wide variety of indicator instruments such as a clock, speedometer, etc. as mentioned in this paper improves driving safety in that the driver does not have to divert his attention and visual eye contact downward to see a normal instrument cluster.
Abstract: An improved rear view mirror which may contain any of a wide variety of indicator instruments such as a clock, speedometer, etc. Use of this improved mirror improves driving safety in that the driver does not have to divert his attention and visual eye contact downward to see a normal instrument cluster. Instruments are easily connected and installed and, if necessary, removed by means of removable back plate and sliding pressure contacts. The instruments may be illuminated for ease of night time viewing.
TL;DR: A rear view mirror for a motor vehicle comprising a two-way mirror in which a tinted glass plate is mounted flush against a housing on one side with a rim bracket designed to keep out all light is described in this article.
Abstract: A rear view mirror for a motor vehicle comprising a two-way mirror in which a tinted glass plate is mounted flush against a housing on one side with a rim bracket designed to keep out all light. The housing incorporates instruments and devices to show information by LED's including a digital clock, and a radar detector.
TL;DR: In this article, a high-speed hybrid clock recovery circuit composed of an analog phase-locked loop (PLL) and a digital PLL (DPLL) for disk drive applications is described.
Abstract: A high-speed hybrid clock recovery circuit composed of an analog phase-locked loop (PLL) and a digital PLL (DPLL) for disk drive applications is described. The chip operates at a maximum data rate of 33 MHz from a single 5-V power supply and achieves fast acquisition, a decode window of 95% of full window width, effective sampling jitter of 100-ps rms, and an effective input sampling rate of 1 GHz. The ring oscillator in the analog PLL shows a 62 p.p.m./ degrees C temperature coefficient (TC) and 4.5%/V supply sensitivity of free-running frequency. The total power dissipation is about 600 mW, and the active area is 30000 mil/sup 2/ in a 2- mu m single-poly double-metal n-well CMOS process. >