Abstract: The present invention relates to a method for fabricating a semiconductor device. For improving the adhesion between a copper-containing interconnect element and a diffusion barrier on top of it, a first dielectric layer (108) of a first dielectric material is deposited on an exposed surface (102.1) of the interconnect element. Susequently, particles (110) are implanted into the first dielectric layer and the interconnect element (102) so as to let the interconnect material mix with the first dielectric material in a first interface region (102.2) between the interconnect element and the first dielectric layer.

Abstract: A thin diffusion barrier was self-formed by annealing at an interface between a Cu-Mn alloy film and a SiO2 substrate. The growth of the barrier layer followed a logarithmic rate law, which represents field-enhanced growth mechanism in the early stage and self-limiting growth behavior in the late stage. The barrier layer was stable at 450 °C for 100 h and at 600 °C for 10 h. The interface diffusivity was estimated from the morphology change of the barrier layer at 600 °C and was found to be smaller than the grain-boundary diffusivity of bulk Cu.

Abstract: High-power density and high durability are the main targets for solid oxide fuel cell (SOFC) development at Forschungszentrum Julich. Power density has been further increased by variation of the material composition of perovskite-based cathodes (Sr content, Co content, substoichiometry) and by optimization of the diffusion barrier (Gd-substituted ceria) between an electrolyte and a cathode. The application of dense diffusion barrier layers significantly improved the performance. The associated avoidance of SrZrO3 formation, however, contributed only to a small extent to the improvement of durability of SOFCs with LSCF cathodes. The redox stability of anode-supported SOFCs has been addressed in two ways: (a) conventional Ni/yttria-stabilized zirconia anode substrates have been investigated to explore the limits of re-oxidation and to determine the degree of oxidation at which no damages occur. (b) Alternative anodes and anode substrates are under development, which basically consist of mixed-conducting ceramics. Avoiding the high amount of nickel decreases the probability of failure, but does not automatically lead to redox-stable anodes. The differences in the materials' properties of such ceramics in oxidizing and reducing environment are addressed.

Abstract: The authors developed a growth method for carbon nanotubes (CNTs) by using a resist-assisted patterning process. The CNTs can be grown directly on the patterned catalyst surface without a diffusion barrier. The growth-site patterns were fabricated on a nickel/silicon (Ni∕Si) substrate by a conventional lithography method using a photopatternable resist. The growth mechanism of the CNTs without diffusion barrier was confirmed by Raman spectroscopy and transmission-electron microscope measurement. The carbon-network formation during forming the process is a key parameter for CNT growth. The technique will be applicable to a low-cost fabrication process of electron-emitter arrays.

Abstract: Auger depth profiling technique and X-ray diffraction analysis have been employed to study the interdiffusion in vacuum-deposited copper–nickel bilayer thin films. An adaptation of the Whipple model was used to determine the diffusion coefficients of both nickel in copper and copper in nickel. The calculated diffusion coefficient is (2.0×10 −7 cm 2 /s)exp(−1.0 eV/kT) for nickel in copper, and (6×10 −8 cm 2 /s)exp(−0.98 eV/kT) for copper in nickel. The difference between the diffusion parameters obtained in the present work and those extracted by other investigators is attributed essentially to the difference in the films microstructure and to the annealing ambient. It is concluded that interdiffusion in the investigated films is described by type-B kinetics in which rapid grain-boundary diffusion is coupled to defect-enhanced diffusion into the grain interior. The present data raise a question about the effectiveness of nickel as a diffusion barrier between copper and the silicon substrate.

Abstract: Copper (titanium) [Cu(Ti)] films with low titanium (Ti) concentration were found to form thin Ti-rich barrier layers at the film/substrate interfaces after annealing, which is referred to as self-formation of the barrier layers. This Cu(Ti) alloy was one of the best candidates for interconnect materials used in next-generation ultra-large-scale integrated (ULSI) devices that require both very thin barrier layers and low-resistance interconnects. In the present paper, in order to investigate the influences of annealing ambient on resistivity and microstructure of the Cu alloys, the Cu(7.3at.%Ti) films were prepared on the SiO2 substrates and annealed at 500°C in ultra-high vacuum (UHV) or argon (Ar) with a small amount of impurity oxygen. After annealing the film at 500°C in UHV, the resistivity was not reduced below 16 μΩ-cm. Intermetallic compounds of Cu4Ti were observed to form in the films and believed to cause the high resistivity. However, after subsequently annealing in Ar, these compounds were found to decompose to form surface TiO x and interfacial barrier layers, and the resistivity was reduced to 3.0 μΩ-cm. The present experiment suggested that oxygen reactive to titanium during annealing played an important role for both self-formation of the interfacial barrier layers and reduction of the interconnect resistivity.

Abstract: Mo∕W–N bilayer thin film structures deposited on Si using sputtering have been studied as a copper diffusion barrier. The thermal stability of the barrier structure after annealing Cu∕Mo∕W–N∕⟨Si⟩ samples in N2 for 5min is studied using x-ray diffraction (XRD), scanning electron microscopy/energy dispersive spectroscopy, and four point probe measurements. The failure of the barrier structure is indicated by the abrupt increase in sheet resistance value and the formation of Cu3Si phase as probed by XRD. Our results suggest that the Mo (5nm)∕W–N (5nm) barrier is stable and can prevent the formation of Cu3Si at least up to 775°C.

Abstract: ZrSiN film was selected as diffusion barrier of titanium porcelain interface and sputtered on polished titanium substrate with RF reactive magnetron sputtering. XRD, XPS and TEM results revealed that the ZrSiN diffusion barrier is a nano-composite that consists of nano-crystallite ZrN and amorphous-like SiN x phase. The results also showed that after simulated porcelain sintering thermocycles the surface of Ti substrate without ZrSiN diffusion barrier appears Ti oxide, however, the surface of Ti substrate with ZrSiN diffusion barrier appears no Ti oxides and only Zr, Si N and O. This proves that ZrSiN diffusion barrier protect the Ti substrate against oxidation during porcelain sintering. The results of three-point bending test also proved that ZrSiN diffusion barrier significantly improves the bonding strength between Ti substrate and porcelain. The ZrSiN diffusion barrier with higher Si content results in higher bonding strength of the Ti/porcelain. This indicates that amorphous Si–N phase of ZrSiN diffusion barrier improves its barrier property.

Abstract: The ability to integrate carbon nanotubes, especially single-walled carbon nanotubes, seamlessly onto silicon would expand the range of applications considerably. Though direct integration using chemical vapor deposition is the simplest method, the growth of single-walled carbon nanotubes on bare silicon and on ultra-thin oxides is greatly inhibited due to the formation of a non-catalytic silicide. Using x-ray photoelectron spectroscopy, we show that silicide formation occurs on ultra-thin oxides due to thermally activated metal diffusion through the oxide. Silicides affect the growth of single-walled nanotubes more than multi-walled nanotubes due to the increased kinetics at the higher single-walled nanotube growth temperature. We demonstrate that nickel and iron catalysts, when deposited on clean silicon or ultra-thin silicon dioxide layers, begin to form silicides at relatively low temperatures, and that by 900C, all of the catalyst has been incorporated into the silicide, rendering it inactive for subsequent single-walled nanotube growth. We further show that a 4 nm silicon dioxide layer is the minimum diffusion barrier thickness which allows for efficient single-walled nanotube growth.

Abstract: Films having high hermeticity and a low dielectric constant can be used as copper diffusion barrier films, etch stop films, CMP stop films and other hardmasks during IC fabrication. Hermetic films can protect the underlying layers, such as layers of metal and dielectric, from exposure to atmospheric moisture and oxygen, thereby preventing undesirable oxidation of metal surfaces and absorption of moisture by a dielectric. Specifically, a bi-layer film having a hermetic bottom layer composed of hydrogen doped carbon and a low dielectric constant (low-k) top layer composed of low-k silicon carbide (e.g., high carbon content hydrogen doped silicon carbide) can be employed. Such bi-layer film can be deposited by PECVD methods on a partially fabricated semiconductor substrate having exposed layers of dielectric and metal.

Abstract: We report on the formation of low-resistance and thermally stable indium tin oxide (ITO) Ohmic contacts on p‐GaN using a strained p‐InGaN (5nm) layer. Unlike as-deposited ITO contacts on p‐GaN, the as-deposited contacts to a strained p‐InGaN∕p‐GaN layer exhibit Ohmic behavior. The current-voltage characteristics of the ITO∕InGaN∕GaN contacts are further improved upon annealing at 550°C for 1min and the specific contact resistance is 3.2(±0.8)×10−5Ωcm2. In addition, the contact resistivity and surface morphology of the ITO∕InGaN∕GaN contacts annealed for 30min are only slightly increased, confirming the thermal stability of this scheme. Based on the electrical and Auger spectroscopic data, the low contact resistivity and thermal stability of the ITO∕InGaN∕GaN contacts are described in terms of the polarization effect, increased acceptor concentration, and formation of diffusion barrier layer at the interface.

Abstract: Protective self aligned buffer (PSAB) layers are layers of material that are selectively formed at the surface of metal layers in a partially fabricated semiconductor device. In a Damascene interconnect, PSAB layer typically resides at an interface between the metal layer and a dielectric diffusion barrier layer. PSAB layers promote improved adhesion between a metal layer and an adjacent dielectric diffusion barrier layer. Further, PSAB layers can protect metal surfaces from inadvertent oxidation during fabrication process. A PSAB layer may be formed entirely within the top portion of a metal layer, by, for example, chemically converting metal surface to a thin layer of metal silicide. Thickness of PSAB layers, and, consequently resistance of interconnects can be controlled by partially passivating metal surface prior to formation of PSAB layer. Such passivation can be accomplished by controllably treating metal surface with a nitrogen-containing compound to convert metal to metal nitride.

Abstract: A diffusion-barrier-coating system having a duplex structure comprised of an inner Re(W)–Cr–Ni layer and an outer Ni-aluminide layer was formed on a fourth generation, single-crystal Ni-base superalloy by using electroplating of Re(Ni) and Ni(W) films, Al- and Cr- (high-Cr and low-Cr) pack cementations, and a combination of the two treatments. With the ReW-high-Cr coating, fine needle- or plate-like precipitates formed in the alloy substrate below the inner Re(W, Cr, Ni) layer, while there was little of this precipitate with the ReW-low-Cr pack-cementation coating. The inner, Re-base alloy layer in the ReW-high-Cr coating was identified to be a σ-(Re,Cr,W,Ni) phase, while the inner layer of the ReW-low-Cr was a mixture of σ-(Re,Cr,W,Ni) and δ-Re(Cr,W,Ni) phases. After heating the coated alloys at 1,150 °C for 100 h in air, the outer Al reservoir layer became β-NiAl containing (31–33)Al with α-Cr particles and fine precipitates of γ′-Ni3Al with both the ReW-high-Cr and ReW-low-Cr treatments. In the case of the ReW-high-Cr coating there were numerous light-colored, needle-like precipitates formed deep in the alloy substrate under the inner layer, while in the case of the ReW-low-Cr coating γ′ appeared near the inner layer. It was found that the inner, Re-base alloy layer acted as a diffusion barrier, and that its structure was maintained with little change in composition after 100 h of oxidation at 1,150 °C.

Abstract: In this work, we report on the interdiffusion of Ge and Si in Ti3SiC2 and Ti3GeC2, as well as that of Nb and Ti in Ti2AlC and Nb2AlC. The interdiffusion coefficient, Dint, measured by analyzing the diffusion profiles of Si and Ge obtained when Ti3SiC2–Ti3GeC2 diffusion couples are annealed in the 1473–1773 K temperature range at the Matano interface composition (≈Ti3Ge0.5Si0.5C2), was found to be given by Dint increased with increasing Ge composition. At the highest temperatures, diffusion was halted after a short time, apparently by the formation of a diffusion barrier of TiC. Similarly, the interdiffusion of Ti and Nb in Ti2AlC–Nb2AlC couples was measured in the 1723–1873 K temperature range. The Dint for the Matano interface composition, viz. ≈(Ti0.5,Nb0.5)2AlC, was found to be given by At 1773 K, the diffusivity of the transition metal atoms was ≈7 times smaller than those of the Si and Ge atoms, suggesting that the former are better bound in the structure than the latter.

Abstract: Ultrathin TaSiC amorphous films prepared by magnetron cosputtering using TaSi2 and C targets on Si(100), in a sandwiched scheme Si(100)∕TaSiC(5nm)∕Cu, were evaluated for barrier performance in copper metallization. Optimizing carbon content maximizes thermal stability of the films as depicted by sheet-resistance, x-ray diffraction, and transmission electron microscopy examination. The stability temperatures of 700°C (24at.% C) and 750°C (34at.% C) have been systematically verified and discussed. Since Ta, Si, and C are compatible with integrated circuit (IC) processing, the TaSiC films are readily applicable for sub-65-nm IC production.

Abstract: A wet process based on electroless deposition is proposed for the formation of a diffusion barrier layer for Cu wiring in ultra-large scale integration (ULSI) technology. The diffusion barrier layer is formed on a low-dielectric constant (low-k) inter level film. In this process, a Pd-activated self-assembled monolayer as a seed/adhesion layer was used as a key step to allow electroless deposition on a dielectric film. The effectiveness of this approach was demonstrated by depositing an electroless NiB layer as the diffusion barrier layer. The electrolessly deposited NiB layer showed a uniform surface, a small grain size, and a high adhesion when deposited on various common inter level dielectric materials with low dielectric constant. The electrolessly deposited NiB layer formed on the low-k dielectric film by this method showed a high thermal stability of the effectiveness as a barrier to Cu diffusion at temperatures up to 400°C for 30 min. The electroless process was found to be reproducible and did not affect dielectric properties of the underlying insulator.

Abstract: A solar cell that is readily manufactured using processing techniques which are less expensive than microelectronic circuit processing. In preferred embodiments, printing techniques are utilized in selectively forming masks for use in etching of silicon oxide and diffusing dopants and in forming metal contacts to diffused regions. In a preferred embodiment, p-doped regions and n-doped regions are alternately formed in a surface of the wafer through use of masking and etching techniques. Metal contacts are made to the p-regions and n-regions by first forming a seed layer stack that comprises a first layer such as aluminum that contacts silicon and functions as an infrared reflector, second layer such titanium tungsten that acts as diffusion barrier, and a third layer functions as a plating base. A thick conductive layer such as copper is then plated over the seed layer, and the seed layer between plated lines is removed. A front surface of the wafer is preferably textured by etching or mechanical abrasion with an IR reflection layer provided over the textured surface. A field layer can be provided in the textured surface with the combined effect being a very low surface recombination velocity.

Abstract: Solder bump structures, which comprise a solder bump on a UBM structure, are provided for operation at temperatures of 2500C and above. According to a first embodiment, the UBM structure comprises layers of Ni-P, Pd-P, and gold, wherein the Ni-P and Pd-P layers act as barrier and/or solderable/bondable layers. The gold layer acts as a protective layer. According to second embodiment, the UBM structure comprises layers of Ni-P and gold, wherein the Ni-P layer acts as a diffusion barrier as well as a solderable/bondable layer, and the gold acts as a protective layer. According to a third embodiment, the UBM structure comprises: (i) a thin layer of metal, such as titanium or aluminum or Ti/W alloy; (ii) a metal, such as NiV, W, Ti, Pt, TiW alloy or Ti/W/N alloy; and (iii) a metal alloy such as Pd-P, Ni-P, NiV, or TiW, followed by a layer of gold. Alternatively, a gold, silver, or palladium bump may be used instead of a solder bump in the UBM structure.

Abstract: Metal seed layers are deposited on a semiconductor substrate having recessed features by a method that involves depositing a first portion of seed layer material, subsequently selectively resputtering the deposited seed layer material in the presence of exposed diffusion barrier material, and, depositing a second portion of the seed layer material Resputtering operation improves seed layer coverage on the recessed feature sidewalls by redistributing seed layer material within the feature Resputtering, however, sometimes exposes an underlying diffusion barrier material at the feature bottom and at the top corners of the feature In order to prevent inadvertent removal of diffusion barrier layer, resputtering is performed under conditions that allow etching of the seed layer material at a rate which is at least five times greater than the etching rate of a diffusion barrier material Selective resputtering is performed by impinging on the wafer substrate with low-energy argon and/or copper ions

Abstract: The properties of Ta–Ge–(O)N as a diffusion barrier for Cu on silicon have been investigated. Ta–Ge–(O)N was deposited on single crystal p‐Si(001) by reactive sputtering. This was followed by in situ deposition of Cu. Diffusion barrier tests were conducted by subsequent annealing of individual samples in Ar atmosphere at higher temperature. The films were characterized by x-ray diffraction, Auger electron spectroscopy, and four-point probe. The results indicate that Ta–Ge–(O)N fails after annealing at 500°C for 1h compared to Ta(O)N which fails after annealing at 400°C for 1h indicating better diffusion barrier properties.

Abstract: A semiconductor device capable of suppressing a threshold shift and a manufacturing method of the semiconductor device. On a high dielectric constant insulating film, a diffusion barrier film for preventing the diffusion of metal elements from the high dielectric constant insulating film to an upper layer is formed. Therefore, the diffusion of the metal elements from the high dielectric constant insulating film to the upper layer can be prevented. As a result, a reaction and bonding between the metal elements and a Si element in a gate electrode can be suppressed near a boundary between an insulating film and the gate electrode.