Abstract: This study focuses on the oxygen permeability of SiOx thin films on polyethyleneterephtalate (PET) produced by plasma-enhanced chemical vapor deposition (PECVD) from oxygen-diluted hexamethyldisiloxane (HMDSO). The versatile PECVD set-up, equipped with two plasma sources (remote microwave and direct radio frequency), allows the deposition of films with variable morphologies and compositions. The deposits were analyzed by XPS, ellipsometry, and atomic force microscopy (AFM). Curve fitting of the Si 2p peak in X-ray photoelectron spectra (XPS) provided information about the chemical binding states of the silicon atoms. The results clearly show that the oxygen transmission rate (OTR) depends highly on the film structure, whereas the chemical composition has only little effect. In order to achieve the desired dense and smooth film structure, it is necessary to have a high substrate bias, which promotes ion bombardment of the film surface during growth. OTR values down to 0.2 cm3 (STP) m− 2 day− 1, corresponding to a barrier improvement factor of 500, have been achieved.

Abstract: An intriguing growth morphology of Pb islands on a Si(111) surface is observed in our STM experiments: the growth of a Pb layer on Pb islands with unstable heights starts from the periphery and moves towards the center, while the nucleation of the next layer on stable Pb islands starts away from the periphery. Using first-principles total energy calculations, we have studied the diffusion barriers of Pb adatoms on a freestanding Pb(111) film as a function of film thickness. The diffusion barriers are found to be very low (<60 meV), and a bi-layer oscillation due to the quantum size effect (QSE) is observed, with a lower barrier on the odd-layered, relatively unstable Pb films. The diffusion barrier difference between the odd- and even-layered film is as large as 40 meV. The observed unusual growth can be attributed to this big difference in the diffusion barriers due to QSE.

Abstract: Methods and devices are provided for absorber layers formed on foil substrate. In one embodiment, a method of manufacturing photovoltaic devices may be comprised of providing a substrate comprising of at least one electrically conductive aluminum foil substrate, at least one electrically conductive diffusion barrier layer, and at least one electrically conductive electrode layer above the diffusion barrier layer. The diffusion barrier layer may prevent chemical interaction between the aluminum foil substrate and the electrode layer. An absorber layer may be formed on the substrate. In one embodiment, the absorber layer may be a non-silicon absorber layer. In another embodiment, the absorber layer may be an amorphous silicon (doped or undoped) absorber layer. Optionally, the absorber layer may be based on organic and/or inorganic materials.

Abstract: Ruthenium-titanium nitride (Ru-TiN) thin films were grown by plasma-enhanced atomic layer deposition (PEALD) at a growth temperature of 200°C. For the Ru-TiN PEALD, Ru and TiN were sequentially deposited to intermix TiN with Ru. The composition of Ru-TiN films was controlled by changing the number of deposition cycles allocated to Ru, while the number of deposition cycles for TiN was fixed to one cycle. The microstructures of Ru-TiN films changed from polycrystalline to amorphous, as the intermixing ratio of Ru increased in the deposited Ru-TiN films. The resistivity of the Ru-TiN film was abruptly increased by adding Ru at the first stage, but after showing a peak resistivity, it decreased with the intermixing ratio of Ru in the films. Especially, the film of Ru 0.67 -(TiN) 0.33 showed an electrical resistivity of 190 μΩ cm. As a Cu diffusion barrier layer, amorphous Ru-TiN films showed a superior copper diffusion barrier property to TiN or Ru itself, which had a polycrystalline structure. Moreover, Ru-TiN films showed a good adhesion to both chemical vapor deposition copper and an underlayer of SiO 2 .

Abstract: eNASA-Glenn Research Center, Cleveland, Ohio 44135, USA Reduced operating temperatures 600–800°C of solid oxide fuel cells SOFCs may enable the use of inexpensive ferritic steels as interconnects. Due to the demanding SOFC interconnect operating environment, protective coatings are gaining attention to increase long-term stability. In this study, large area filtered arc deposition and hybrid filtered arc deposition-assisted electron beam physical vapor deposition technologies were used to deposit two-segment coatings with Cr-Co-Al-O-N-based bottom segment and Mn-Co-O top segment. The bottom segment serves as a diffusion barrier and bond segment, while the top segment is meant to increase electrical conductivity and inhibit Cr volatility. Coatings were deposited on ferritic steel and subsequently annealed in air for various time intervals. Surface oxidation was investigated using Rutherford backscattering spectrometry, scanning electron microscopy, and energy-dispersive spectrometry analyses. Cr volatilization was evaluated using a transpiration apparatus and inductively coupled plasma-mass spectrometry analysis of the resultant condensate. Electrical conductivity area specific resistance, ASR, was studied as a function of time using the four-point technique. Significant improvement in oxidation resistance, Cr volatility, and ASR were observed in the coated versus uncoated samples. Transport mechanisms for various oxidizing species and coating diffusion barrier properties are discussed.

Abstract: Ti–Si–N coatings were deposited on M2 steel by arc evaporation using a Ti–Si composite target in an industrial reactor. The films structure before and after heat treatment at 700 °C was characterised by XRD. In addition, two types of quantitative experiments were performed in thermobalance: oxidation rate was deduced from isothermal thermogravimetric analyses at 800 °C, while the temperature of oxidation beginning ( Tc ) was measured in dynamic mode. Tc was then calculated by a mathematical approximation based on the non-linear least square. The results were compared to those obtained using TiN and SiN x standards. Depending on the deposition conditions, ternary films have been deposited with an atomic ratio Si/Ti of 0.10 and 0.15. The hardness of the films was close to 40 GPa. Only the TiN phase was detected by XRD. The mean crystal size was estimated to be in the 6–8 nm range, which suggested the nanocomposite nature of the coatings. After air oxidation at 700 °C, it was found that this crystal size was not affected by the thermal treatment, indicating a good thermal stability of the structure. Moreover, incorporation of silicon into TiN-based coatings led to a drastic decrease of their oxidation rate, together with a shift of 200 °C of Tc . The high resistance of oxidation of Ti–Si–N films at elevated temperature is attributable to the network of refractory SiN x , which acted as a diffusion barrier for oxygen and insulated TiN nanograins from the aggressive atmosphere.

Abstract: An intriguing growth morphology of Pb islands on a Si(111) surface is observed in our STM experiments: the growth of a Pb layer on Pb islands with unstable heights starts from the periphery and moves towards the center, while the nucleation of the next layer on stable Pb islands starts away from the periphery. Using first-principles total energy calculations, we have studied the diffusion barriers of Pb adatoms on a freestanding Pb(111) film as a function of film thickness. The diffusion barriers are found to be very low (<60 meV), and a bi-layer oscillation due to the quantum size effect (QSE) is observed, with a lower barrier on the odd-layered, relatively unstable Pb films. The diffusion barrier difference between the odd- and even-layered film is as large as 40 meV. The observed unusual growth can be attributed to this big difference in the diffusion barriers due to QSE.

Abstract: An integrated circuit (IC) may include a substrate, a first dielectric layer adjacent the substrate, and at least one trench in the first dielectric layer. The IC may also include a metal liner within the at least one trench, and a first conductive region including copper within the at least one trench. A cap layer including metal may be provided on the first conductive region. A second dielectric layer may be over the first conductive region and the cap layer. A dielectric etch stop and diffusion barrier layer may be over the second dielectric layer, and a via may be over the first conductive region and through the second dielectric layer and the cap layer. A diffusion barrier layer may be on sidewalls of the via, and an alloy seed layer including copper and at least one of tantalum, molybdenum, chromium, and tungsten may be over the diffusion barrier. The alloy seed layer may also be over the dielectric etch stop and diffusion barrier layer, and the alloy seed layer may be in contact with the first conductive region.

Abstract: An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx- or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.

Abstract: Described herein are metal gate electrode stacks including a low resistance metal cap in contact with a metal carbonitride diffusion barrier layer, wherein the metal carbonitride diffusion barrier layer is tuned to a particular work function to also serve as a work function metal for a pMOS transistor. In an embodiment, the work function-tuned metal carbonitride diffusion barrier prohibits a low resistance metal cap layer of the gate electrode stack from migrating into the MOS junction. In a further embodiment of the present invention, the work function of the metal carbonitride barrier film is modulated to be p-type with a pre-selected work function by altering a nitrogen concentration in the film.

Abstract: To increase the lifetime and the ductility of the brittle diffusion layer Al3Ti, utilized as a protective coating against oxidation at high temperature, a trialuminide coating process was developed on commercial-purity Ti by hot-dipping aluminizing baths containing Ni, Si and Cr as added alloying elements and followed by two vacuum annealing treatments. The first was carried out at 700 °C for 48 h to transform the Al coating into Al3Ti, the second up to 870 °C for 170 h to complete the formation of aluminide layers, to verify the sufficient thermal stability of the diffusion coatings under the α–β Ti transition temperature and to complete the diffusion of the ternary Ni, Si and Cr added to the aluminizing baths. Compared to aluminide coatings composed by Al3Ti, AlTi and AlTi3 obtained by pure aluminium in the aluminizing bath after annealing at 870 °C, the as-coated aluminized layers obtained by the presence of Ni, Si and Cr in aluminizing baths, after annealing at 870 °C, shaped also as Si-rich and Ni-rich phases at the Al3Ti/AlTi interface. In the case of Si, as an added alloying element, the Si-rich phase may act on the Al inward diffusion and the outward Ti diffusion inside the coating forming a diffusion barrier and prolonging the lifetime of the protective aluminides. In the case of Ni and Cr addition, there is a possibility of transforming the brittle tetragonal DO22 structure to a cubic L12 Al3Ti structure with reduced hardness and increased cracking resistance of the transformed protective diffusion aluminide. This study showed that the non-structural Al3Ti coating layer, owing to its brittleness and hardness, can be transformed into a structural phase with lower hardness and brittleness up to 870 °C and that the formation of diffusion barriers, which depress the Al inward diffusion and the outward Ti diffusion, can reduce the decomposition of the unstable aluminides at high temperatures, prolonging their lifetime.

Abstract: Dysprosium scandate (DyScO3) thin films were deposited on Si substrates using metal-organic chemical vapor deposition. Individual source precursors of Dy and Sc were used and deposition temperatures ranged from 480to700°C. Films were amorphous with low root mean square roughness (⩽2A) and were stable up to 1050°C annealing. Electrical characterization yielded C-V curves with negligible hysteresis (<10mV), high dielectric constant (∼22), and low leakage currents. The electrical properties of the DyScO3∕SiOx∕Si stacks were stable up to 800°C for films on native oxide; however, this limit increased to 900°C for films on special chemically grown oxide, suggesting further improvement with proper diffusion barrier.

Abstract: A method of forming a capping layer on a copper interconnect line (14). The method comprises providing a layer (20) of Aluminium over the interconnect line (14) and the dielectric layer (10) in which it is embedded. This may be achieved by deposition or chemical exposure. The structure is then subjected to a process, such as annealing or further chemical exposure, in an environment containing, for example, Nitrogen atoms, so as to cause indiffusion of Al into the copper line (14) and nitridation to form a diffusion barrier 26 of the intermetallic compound CuAlN.

Abstract: An inter-metal dielectric (IMD) fill process includes depositing an insulating nanolaminate barrier layer. The nanolaminate is preferably an oxide liner formed by using an alternating layer deposition process. The layer is highly conformal and is an excellent diffusion barrier. Gaps between metal lines are filled using high density plasma chemical vapor deposition with a reactive species gas. The barrier layer protects the metal lines from shorts between neighboring layers. The resulting structure has substantially uneroded metal lines and an insulating IMD fill.

Abstract: Diffusion barrier properties of ultrathin Ta 2 O 5 and TiO 2 films deposited by the atomic layer deposition (ALD) method were investigated. The oxide films were deposited using well-defined deposition processes with metal alkoxides and water as precursors. Tantalum oxide films were deposited from tantalum pentaethoxide and water and titanium dioxide films from titanium tetramethoxide and water, both at 240°C. The films examined in the diffusion barrier tests were in the thickness range of 1 - 4 nm. The breakdown temperatures of the annealed Cu/barrier/Si structures were determined from the increase in the sheet resistance, X-ray diffraction data, and etch-pit test results. From the studied barrier films, the 3-nm-thick titanium dioxide film was found to possess the best resistance to copper diffusion as the first etch pits were observed only after the annealing at 650°C.

Abstract: Tantalum nitride (Ta 2 N) films deposited at various substrate temperatures onto silicon (001) substrates can produce amorphous and crystalline phase with different preferred orientations. Subsequently, the viability of employing them as the diffusion barriers between copper and silicon is investigated by annealing at various temperatures for 30 min. The characterization of the thin films was carried out by four-point probe and X-ray diffraction. The results indicate that the thermal stability of Ta 2 N with Cu and Si are dependent on the crystallinity of Ta 2 N. Ta 2 N phase with the highest (002) preferred orientation exhibits the highest structural stability to prevent copper diffusion more effectively.

Abstract: The present invention provides improved methods of depositing tungsten-containing films on substrates, particularly on silicon substrates. The methods involve depositing an interfacial or “flash” layer of tungsten on the silicon prior to deposition of tungsten nitride. The tungsten flash layer is typically deposited by a CVD reaction of a tungsten precursor and a reducing agent. According to various embodiments, the tungsten flash layer may be deposited with a high reducing agent to tungsten-precursor ratio and/or at low temperature to reduce attack by the tungsten precursor. In many cases, the substrate is a semiconductor wafer or a partially fabricated semiconductor wafer. Applications include depositing tungsten nitride as (or as part of) a diffusion barrier and/or adhesion layer for tungsten contacts.

Abstract: To suppress interdiffusion between the coating and alloy substrate in addition to ensuring slow oxide growth at very high temperatures advanced coatings were developed, and they were classified into four groups, (1) the diffusion barrier coating with a duplex layer structure, an inner σ−(Re-Cr-Ni) phase as a diffusion barrier and outer Ni aluminides as an aluminum reservoir formed on a Ni based superalloy, Hastelloy X, and Nb-based alloy. (2) the up-hill diffusion coating with a duplex layer structure, an inner TiAl2 + L12 and an outer β-NiAl formed on TiAl intermetallic and Ti-based heat resistant alloys by the Ni-plating followed by high Al-activity pack cementation. (3) the chemical barrier coating with a duplex layer structure, an inner* γ + β + Laves three phases mixture as a chemical diffusion barrier and an outer Al-rich γ-TiAl as an Al reservoir formed by the two step Cr / Al pack process. (4) the self-formed coating with the duplex structure, an inner α-Cr layer as a diffusion barrier and an outer β-NiAl as an Al-reservoir on Ni-(20
50)at% Cr alloy changed from the δ-Ni2Al3 coating during oxidation at high temperature. The oxidation properties of the coated alloys were investigated at temperatures between 1173 and 1573K in air for up to 1,000 hrs (10,000 hrs for the up-hill diffusion coating). In the diffusion barrier coating the Re-Cr-Ni alloy layer was stable, existing between the Ni-based superalloy (or Hastelloy X) and Ni aluminides containing 12
50at%Al when oxidized at 1423K for up to 1800ks. It was found that the Re-Cr-Ni alloy layer acts as a diffusion barrier for both the inward diffusion of Al and outward diffusion of alloying elements in the alloy substrate. In the chemical barrier coating both the TiAl2 outermost and Al-rich γ-TiAl outer layers maintained high Al contents, forming a protective Al2O3 scale, and it seems that the inner, γ, β, Laves three phase mixture layer suppresses mutual diffusion between the alloy substrate and the outer/outermost layers.

Abstract: A study of copper (Cu) diffusion into silicon substrates through Ta nitride (TaN) and tantalum (Ta/TaN) layers was investigated based on an experimental approach. TaN x and Ta/TaN x thin films were deposited by radiofrequency sputtering under argon (Ar) and Ar-nitrogen (N) plasma. The influence of the N2 partial pressure on the microstructure and the electrical properties is reported. X-ray diffraction patterns showed that the increase of the N2 partial pressure, from 2 to 10.7%, induces a change in the composition of the δTaN phase, from TaN to TaN1.13, as well as an evolution of the dominant crystallographic orientation. This composition change is related to a drastic increase of the electrical resistivity over a N2 partial pressure of 7.3%. The efficiency of TaN layers and Ta/TaN multilayer diffusion barriers was investigated after annealing at temperatures between 600 and 900 °C in vacuum. Secondary ion mass spectrometry profiles showed that Cu diffuses from the surface layer through the TaN barrier from 600 °C. Cu diffusion mechanisms are modified in the presence of a Ta sublayer.

Abstract: Gold eutectic bonding of silicon wafers is a good candidate for wafer level vacuum packaging of vibrating MEMS: in this paper we investigated several e-beam evaporated metallizations stacks including a titanium adhesion layer, an optional diffusion barrier (Ni or Pt) and a gold film for eutectic bonding on Si and SiO2/Si wafers. Interdiffusion in the multilayers for annealing temperatures (380–430°C) larger than the Au–Si eutectic temperature (363°C) and times corresponding to a bonding process was characterized by RBS, roughness and resistivity measurements. Au/Pt/Ti and Au/Ti/SiO2 were found to have the best characteristics for bonding. This was confirmed by bonding experiments.

Abstract: The capability of a cobalt-phosphorous [Co(P)] layer, which was grown via the electroless plating process, to serve as the diffusion barrier of lead-tin (PbSn) solder was investigated in this work. The Auger electron spectroscopy (AES) and energy dispersive spectrometry (EDX) indicated that the phosphorous contents in Co(P) films decrease with increasing film thickness and that the average contents are no less than 8.7 at.% for the specimens prepared in this work. X-ray diffraction in conjunction with composition analyses revealed that the electroless Co(P) layer was a mixture of amorphous and nanocrystalline structures; however, the AES depth profile and subsequent analyses indicated that the first-formed Co(P) layer should be amorphous because it contains as much as 18 at.% P. This implied a good barrier capability for electroless Co(P) because, as revealed by EDX line scan, the Sn and Cu atoms could not penetrate the Co(P) layer after the PbSn/Cu/Co(P)/Cu/Ti/Si sample was subjected to annealing at 250°C in a forming gas ambient for 24 h. The fact that Sn and Cu underlayers could not penetrate the Co layer after such a liquid-state annealing step was evidence that the Co(P) layer may simultaneously serve as a diffusion-barrier interlayer dielectric and as an under-bump metallization for flip-chip copper (Cu) ICs.

Abstract: The growth and formation of Ge nanocrystals embedded into a silicon oxide (SiO2) system synthesized by furnace annealing have been studied based on the Ge content of co-sputtered Ge–SiO2 films. The influence of a silicon oxide diffusion barrier inserted between the co-sputtered film and the substrate on the formation of the Ge nanocrystals is also examined. We found that the effect of Si reduction on the Ge oxides plays an important role in the synthesis of Ge nanocrystals in co-sputtered Ge plus SiO2 samples with high Ge oxide concentration (80%) relative to the elemental Ge concentration (20%). The oxide diffusion barrier influenced the distribution of the nanocrystals by preventing Ge from diffusing into the substrate such that nanocrystals were formed throughout the film. When the Ge concentration was much higher (75%) than the Ge oxide concentration, the contribution from the effect of Si reduction on the Ge oxides in the formation of the nanocrystals is not significant. Again, the oxide diffusion barrier was very effective in preventing Ge atoms from diffusing into the Si substrate, and significant coarsening of the nanoclusters was observed in these samples.

Abstract: A diffusion layer for semiconductor devices is provided. In accordance with embodiments of the present invention, a semiconductor device, such as a transistor, comprises doped regions surrounded by a diffusion barrier. The diffusion barrier may be formed by recessing regions of the substrate and implanting fluorine or carbon ions. A silicon layer may be epitaxially grown over the diffusion barrier in the recessed regions. Thereafter, the recessed regions may be filled and doped with a semiconductor or semiconductor alloy material. In an embodiment, a semiconductor alloy material, such as silicon carbon, is selected to induce a tensile stress in the channel region for an NMOS device, and a semiconductor alloy material, such as silicon germanium, is selected to induce a compressive stress in the channel region for a PMOS device.

Abstract: The authors investigated the effectiveness of atomic layer deposited (ALD) aluminum oxide barrier layer in controlling the interfacial reaction between ALD HfO2 film and Si substrate The HfO2 was observed to form silicate and silicide at its interface with Si during 5min postdeposition annealing in Ar at 800 and 1000°C A 05-nm-thick Al2O3 barrier layer was found to control interfacial reactions between HfO2 and Si during annealing at 800°C, but not at 1000°C, whereas a 15-nm-thick barrier of Al2O3 was needed to prevent interfacial reaction up to an annealing temperature of 1000°C