TL;DR: In this paper, the authors investigated the possibility of the self-forming barrier layer in Cu-Mn alloy thin films deposited directly on SiO2 and found that after annealing at 450°C for 30 min, a Mn containing amorphous oxide layer of 3-4 nm in thickness was formed uniformly at the interface.
Abstract: Advancement of semiconductor devices requires the realization of an ultrathin diffusion barrier layer between Cu interconnect and insulating layers. The present work investigated the possibility of the self-forming barrier layer in Cu–Mn alloy thin films deposited directly on SiO2. After annealing at 450 °C for 30 min, a Mn containing amorphous oxide layer of 3–4 nm in thickness was formed uniformly at the interface. Residual Mn atoms were removed to form a surface oxide layer, leading to a drastic resistivity decrease of the film. No interdiffusion was detected between Cu and SiO2 within the detection limit of x-ray energy dispersive spectroscopy.
TL;DR: A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with Fbased dielectrics etch and Cl- and F-based barrier etch as discussed by the authors.
Abstract: A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.
TL;DR: In this paper, the phase-change barrier prevents diffusion of the phase change material into the isolation material, and the diffusion barrier is replaced by a diffusion barrier for thermally isolating the phasechange material.
Abstract: A memory cell device includes a first electrode, phase-change material adjacent the first electrode, a second electrode adjacent the phase-change material, a diffusion barrier adjacent the phase-change material, and isolation material adjacent the diffusion barrier for thermally isolating the phase-change material. The diffusion barrier prevents diffusion of the phase-change material into the isolation material.
TL;DR: In this article, a low dielectric constant copper diffusion barrier film suitable for use in a semiconductor device and methods for fabricating such a film are presented. But the present paper is limited to the case where the diffusion barrier is formed of a silicon-based material doped with boron.
Abstract: The present invention provides a low dielectric constant copper diffusion barrier film suitable for use in a semiconductor device and methods for fabricating such a film. Some embodiments of the film are formed of a silicon-based material doped with boron. Other embodiments are formed, at least in part, of boron nitride. Some such embodiments include a moisture barrier film that includes oxygen and/or carbon. Preferred embodiments of the copper diffusion barrier maintain a stable dielectric constant of less than 4.5 in the presence of atmospheric moisture.
TL;DR: In this article, a method for selective deposition of self-assembled monolayers to the surface of a substrate for use as a diffusion barrier layer in interconnect structures is provided.
Abstract: A method for selective deposition of self-assembled monolayers to the surface of a substrate for use as a diffusion barrier layer in interconnect structures is provided comprising the steps of depositing a first self-assembled monolayer to said surface, depositing a second self-assembled monolayer to the non-covered parts of said surface and subsequently heating said substrate to remove the first self-assembled monolayer. The method of selective deposition of self-assembled monolayers is applied for the use as diffusion barrier layers in a (dual) damascene structure for integrated circuits.
TL;DR: In this article, the authors evaluated the wettability of Cu on Ru and Ta glue layers as the index of Cu adhesion strength onto glue layers and found that the wetting angle of Cu (43°) on a Ru substrate was three times lower than that of Ta substrate after annealing.
Abstract: The main issue of Cu metallization is the electromigration of Cu through the interface between Cu and the barrier or capping layer. To improve electromigration resistance at the Cu and barrier metal interface, insertion of a glue layer which enhances the adhesion of Cu onto the under layer may be effective. The wettability of Cu on Ru and Ta glue layers was evaluated as the index of Cu adhesion strength onto glue layers. The wetting angle of Cu (43°) on a Ru substrate was three times lower than that of Cu (123°) on a Ta substrate after annealing. Lower wetting angle of Cu on a Ru substrate indicates a good adhesion property between Cu and Ru and may imply a high electromigration resistance. The better Cu wettability of Ru compared to Ta can be explained by the concept of lattice misfit. A Ru(002) plane has lower lattice misfit, which suggests lower interface energy, and enhanced the adhesion of Cu onto Ru. However, the Ru film showed poor Cu diffusion barrier properties, which suggests Ru should be used as a glue layer in combination with another barrier layer.
TL;DR: In this paper, the rear surface of a back contact solar cell is screen printed to minimize p-type contact areas and maximize n-type doped regions on the rear surfaces of a p type substrate.
Abstract: Back contact solar cells including rear surface structures and methods for making same. The rear surface has small contact areas through at least one dielectric layer, including but not limited to a passivation layer, a nitride layer, a diffusion barrier, and/or a metallization barrier. The dielectric layer is preferably screen printed. Large grid areas overlay the dielectric layer. The methods provide for increasing efficiency by minimizing p-type contact areas and maximizing n-type doped regions on the rear surface of a p-type substrate.
TL;DR: In this article, the diffusion barrier properties of deposited TaNx films for Cu interconnects have been studied by thermal stress test based on synchrotron x-ray diffraction.
Abstract: TaNx diffusion barriers with good barrier properties at subnanometer thickness were deposited by plasma-enhanced atomic layer deposition (PE-ALD) from pentakis(dimethylamino)Ta. Hydrogen and/or nitrogen plasma was used as reactants to produce TaNx thin films with a different nitrogen content. The film properties including the carbon and oxygen impurity content were affected by the nitrogen flow during the process. The deposited film has nanocrystalline grains with hydrogen-only plasma, while the amorphous structure was obtained for nitrogen plasma. The diffusion barrier properties of deposited TaN films for Cu interconnects have been studied by thermal stress test based on synchrotron x-ray diffraction. The results indicate that the PE-ALD TaN films are good diffusion barriers even at a small thickness as 0.6nm. Better diffusion barrier properties were obtained for higher nitrogen content. Based on a diffusion kinetics analysis, the nanocrystalline microstructure of the films was responsible for the bette...
TL;DR: In this paper, a batch reactor equipped with a 2.45 GHz slot antenna plasma source and a 13.56 MHz-biased substrate holder, was used to conduct the experiments.
Abstract: This study focuses on the water vapor permeability of plasma enhanced chemical vapor deposited (PECVD) silicon oxide (SiO x ) films. A batch reactor equipped with a 2.45 GHz slot antenna plasma source and a 13.56 MHz-biased substrate holder, was used to conduct the experiments. The remote microwave and the direct radio frequency plasma source can be operated separately or in dual mode. An oxygen plasma was generated and hexamethyldisiloxane (HMDSO) used as monomer. The SiO 2 -like films were deposited onto 12 μm PET film. An increase of RF-power input, oxygen-to-monomer flow rate ratio, layer thickness or decrease of process pressure was found to enhance the gas barrier performance. Compared to uncoated PET films, a maximum reduction of more than a factor of 150 has been achieved for water vapor transmission rate.
TL;DR: In this article, the isothermal oxidation of pure CVD SiC and Si3N4 has been studied for 100 h in dry, flowing oxygen from 1200° to 1600°C in an alumina tube furnace.
Abstract: The isothermal oxidation of pure CVD SiC and Si3N4 has been studied for 100 h in dry, flowing oxygen from 1200° to 1600°C in an alumina tube furnace. Adherent oxide formed at temperatures to 1550°C. The major crystalline phase in the resulting silica scales was alpha-cristobalite. Parabolic rate constants for SiC were within an order of magnitude of literature values. The oxidation kinetics of Si3N4 in this study were not statistically different from that of SiC. Measured activation energies were 190 kJ/mol for SiC and 186 kJ/mol for Si3N4. Silicon oxynitride did not appear to play a role in the oxidation of Si3N4 under the conditions herein. This is thought to be derived from the presence of ppm levels of sodium impurities in the alumina furnace tube. It is proposed that sodium modifies the silicon oxynitride, rendering it ineffective as a diffusion barrier. Material recession as a function of oxide thickness was calculated and found to be low. Oxidation behavior at 1600°C differed from the lower temperatures in that silica spallation occurred after exposure.
TL;DR: In this paper, the atomic layer deposition (ALD) method was used to reduce tantalum and obtain the desired TaN phase, which ensures excellent conformality and large area uniformity of the films.
Abstract: Transition metal nitrides, metal silicides, and metal-silicon-nitrides are considered the most promising diffusion barrier materials for next generation ultra large scale integration (ULSI) microelectronics. The semiconductor industry has long used Ti, Ta, and W based materials, and their material properties have been very well studied. Recently, tantalum-based materials have been attracting particular interest. The barrier properties of materials based on other transition metals have been little studied. In this work, tantalum nitride films were deposited, with four new reducing agents used to reduce tantalum and obtain the desired TaN phase. As well, the deposition of niobium and molybdenum nitride films was investigated. All films were deposited by the atomic layer deposition (ALD) method, which ensures excellent conformality and large area uniformity of the films. The problem in depositing TaN films by ALD is that in volatile tantalum precursors the tantalum usually exists in oxidation state +V which is difficult to reduce to the +III state needed in cubic TaN. The new reducing agents examined in this study were trimethylaluminum (TMA), tert-butylamine (BuNH2), allylamine (allylNH2), and tris(dimethylamino)silane (TDMAS). In addition to reducing tantalum, TMA also acted as a carbon and aluminum source, BuNH2 and allylNH2 as nitrogen sources, and TDMAS as a silicon precursor. ALD of niobium nitride and molybdenum nitride films was studied at lower temperatures than reported earlier. Both NbNx and MoNx films were deposited from the corresponding metal chloride precursors (NbCl5 and MoCl5, respectively) using ammonia as nitrogen source. No additional reducing agent was required. The deposition parameters, compositions, crystallinity, and electrical properties were studied for all deposited films. Barrier characteristics were investigated for Ta(Al)N(C), NbNx, and MoNx films. The work function values were measured for Ta(Si)N films deposited at two different temperatures.
TL;DR: A pinhole-free palladium membrane with a thickness of 3μm has been prepared on the surface of a porous sintered stainless steel tube coated with a thin silver layer as a diffusion barrier as discussed by the authors.
TL;DR: In this paper, an all-wet process for fabrication of Cu wiring on a silicon chip was proposed as a novel ultra-large scale integration (ULSI) interconnect technology for integrated circuits (ICs) applications.
TL;DR: In this article, the authors used arc ion plating (AIP) techniques to create diffusion barriers between NiCoCrAlY overlay coating and Ni-base superalloy DSM I I.
Abstract: Al-O-N and Cr-O-N films were deposited as diffusion barriers between NiCoCrAlY overlay coating and Ni-base superalloy DSM I I using arc ion plating (AIP) techniques. The efficiency of the diffusion barriers was investigated at 1050 and 900 D C. The results showed that the Al-O-N barrier could inhibit the interdiffusion of the alloying elements. Unfortunately, because of deterioration of the mechanical and oxidation properties of the whole system, it could not act as a successful barrier. The Cr-O-N film could act as an active diffusion barrier by changing into an Al-rich oxide layer in high temperature annealing. The achieved interface structure can offer both the barrier properties of a dense ceramic layer and strong bond strength of a reaction-bonding zone. In addition, Cr-O-N films could improve the oxidation properties of the NiCoCrAlY coatings by 18-37%, which were influenced by the original chemical compositions of the Cr-O-N films. C 2004 Elsevier B.V. All rights reserved.
TL;DR: In this paper, an autocatalytic deposition of cobalt is carried out in hypophosphite containing electrolytes at 95°C and pH 8.5, which is used as a barrier metallization for copper in lead-free soldering.
TL;DR: In this paper, the authors showed that the failure temperature of ITO films diffusion barrier (10 nm) was 700°C and showed that ITO film can be considered as diffusion barriers for Cu metallization.
Abstract: Indium tin oxide (ITO) thin films have been proposed as diffusion barriers for ultralarge scale integrated microelectronic devices. High-resolution transmission electron microscopy and electron diffraction showed that in the Cu/ITO/Si film, the 10 nm thick nanocrystalline ITO film layer works effectively as a barrier. Transmission electron microscopy, scanning electron microscopy, sheet resistance measurement, X-ray diffraction, and energy dispersive spectroscopy analyses revealed that ITO was found to be a good diffusion barrier against Cu at least up to 650°C. The failure temperature of ITO films diffusion barrier (10 nm) was 700°C. Our results show that ITO film can be considered as diffusion barriers for Cu metallization.
TL;DR: A flip-chip electrode light-emitting element formed by multilayer coatings where a translucent conducting layer and a highly reflective metal layer acts as flip-Chip electrode for enhancing the LED luminous efficiency is presented in this paper.
Abstract: A flip-chip electrode light-emitting element formed by multilayer coatings where a translucent conducting layer and a highly reflective metal layer acts as flip-chip electrode for enhancing the LED luminous efficiency. The flip-chip electrode light-emitting element includes a translucent substrate, a semiconductor die structure attached on the translucent substrate and made of group III nitride compounds, and an intermediate layer adapted to support the inverted semiconductor die structure on a submount. The flip-chip electrode formed by multiplayer coatings includes a current-spreading transparent conducting layer formed on a top side of the second type semiconductor layer, a highly reflective metal layer formed on a top side of the transparent conducting layer, a metallic diffusion barrier layer formed on a top side of the highly reflective metal layer, and a bonding layer electrically coupled to the intermediate layer and formed on a top side of the barrier layer. Moreover, an ohmic contact layer is formed on the transparent conducting layer. And a passivation layer encloses the die structure for insulating p/n interface and for avoiding the creation of the leakage current.
TL;DR: In this paper, a method of fabricating a semiconductor device including a metal interconnect structure with a conductive region formed in a first dielectric layer, and an overlying, low-k, dielectoric layer is described.
Abstract: A method of fabricating a semiconductor device including a metal interconnect structure with a conductive region formed in a first dielectric layer, and an overlying, low-k, dielectric layer. A via and trench are formed in a dual damascene structure in the overlying dielectric layer, the via aligned with the conductive region and the trench. A sacrificial liner to release organic residues is deposited in the via and over the upper surface of the wafer, over which an organic planarization layer is deposited. The organic planarization layer is removed with a dry plasma etch, followed by a wet clean to remove the sacrificial liner. A diffusion barrier to separate the conductive material from the dielectric layers is deposited over the dual damascene structure and over the upper surface of the wafer. A conductive structure is formed over the diffusion barrier and polished to form an even surface for further processing steps.
TL;DR: A diffusion barrier type coating with a duplex layer structure, an inner σ-(Re, W, Cr, Ni) as a diffusion barrier and outer Ni-aluminide as an Al reservoir, was formed on a Nickel based, single crystal, superalloy (TMS-82 +) and on Hastelloy X as discussed by the authors.
Abstract: A diffusion barrier type coating with a duplex layer structure, an inner σ-(Re, W, Cr, Ni) as a diffusion barrier and outer Ni-aluminide as an Al reservoir, was formed on a Nickel based, single crystal, superalloy (TMS-82 +) and on Hastelloy X. Oxidation properties of both the alloys with or without the diffusion barrier coating were investigated in air under thermal cycling between room temperature and 1423 K for up to 360 ks. The inner σ layer with a composition (at%) of (35–40) Re, (15–20) W, (15–25) Cr and (15–25) Ni was produced by electrodeposition of Ni-70Re and Ni-20W films from aqueous solutions followed by Cr-pack cementation at temperatures between 1473 and 1573 K, and the outer Ni-aluminides of β-(Ni,Cr)Al + γ′-(Ni,Cr)3Al was formed by electrodeposition of a Ni film, followed by Al pack cementation. After the 360 ks oxidation it was found that the structure and composition of both σ layer and alloy substrate were retained with little change. Furthermore, there was little Al in the σ layer. It could be concluded that the Re-based alloys such as σ (Re(W),Cr,Ni) are very promising candidates as a diffusion barrier between the outer Al-reservoir layer and alloy substrate at temperature of 1423 K. It was found that the Re(W)-Cr-Ni acts as a diffusion barrier for both inward diffusion of Al and outward diffusion of alloying elements in the alloy substrate.
TL;DR: The metal capping barrier deposited by the electroless cobalt tungsten boron (CoWB) alloy plating method for ultralarge scale integration applications was investigated in this article.
TL;DR: In this article, the diffusion barrier performances of Mo, Mo-N and Mo/Mo-N metallization layers deposited by sputtering Mo in Ar/N2 atmospheres were studied.
TL;DR: In this article, NbN x thin films were grown by the atomic layer deposition method using niobium chloride and ammonia as precursors and the deposition temperature was varied between 250 and 500 °C.
TL;DR: In this article, barrier properties of thin Au/Ni-P UBM between Cu substrate and Sn 3.5Ag solder were investigated during annealing at 160, 180, and 200 °C in terms of IMC formation.
Abstract: Electroless Ni–P with a thin layer of immersion gold has been considered as a promising under bump metallization (UBM) for low-cost flip–chip technology. However, the presence of P in electroless Ni–P causes complicated interfacial reactions, which affect the reliability of solder joint. In this work, barrier properties of thin Au/Ni–P UBM between Cu substrate and Sn–3.5Ag solder were investigated during annealing at 160, 180, and 200 °C in terms of IMC formation. Multilayer Sn–3.5Ag/Au/Ni–P/Cu sample was prepared by electroless chemical plating and solder reflow for the investigation. Annealing results showed that electroless Ni–P acts as a good barrier for Sn diffusion at 160 and 180 °C. However, it fails to protect the Cu substrate from reacting with Sn at 200 °C. The reason is that the electroless Ni–P layer starts converting into a ternary Ni–Sn–P layer at 200 °C. Complete conversion of the Ni–P layer into Ni–Sn–P, results in the formation of two Cu–Sn intermetallics, Cu 6 Sn 5 and Cu 3 Sn, at the Ni–Sn–P/Cu interface and the formation of (Ni x Cu 1− x ) 6 Sn 5 intermetallic at the Ni 3 Sn 4 /Ni–Sn–P interface.
TL;DR: The use of atomic layer deposition (ALD) to form a conductive titanium nitride layer produces a reliable structure for use in a variety of electronic devices as mentioned in this paper, which can be used as a diffusion barrier underneath another conductor such as aluminum or copper, or as an electro-migration preventing layer on top of an aluminum conductor.
Abstract: The use of atomic layer deposition (ALD) to form a conductive titanium nitride layer produces a reliable structure for use in a variety of electronic devices. The structure is formed by depositing titanium nitride by atomic layer deposition onto a substrate surface using a titanium-containing precursor chemical such as TDEAT, followed by a mixture of ammonia and carbon monoxide or carbon monoxide alone, and repeating to form a sequentially deposited TiN structure. Such a TiN layer may be used as a diffusion barrier underneath another conductor such as aluminum or copper, or as an electro-migration preventing layer on top of an aluminum conductor. ALD deposited TiN layers have low resistivity, smooth topology, high deposition rates, and excellent step coverage and electrical continuity.
TL;DR: In this paper, a strain balance of bi-layer structures on compliant borophosphorosilicate glass (BPSG) was used to achieve high-quality strained-silicon for device applications.
Abstract: Ultrathin, strained-silicon-on-insulator (s-SOI) structures without a residual silicon-germanium (SiGe) underlayer have been fabricated using stress balance of bi-layer structures on compliant borophosphorosilicate glass (BPSG). The bi-layer structure consisted of SiGe and silicon films, which were initially pseudomorphically grown on a silicon substrate and then transferred onto BPSG by a wafer bonding and SmartCut process. The viscous flow of the BPSG during a high-temperature anneal then allowed the SiGe/Si bi-layer to laterally coherently expand to reach stress balance, creating tensile strain in the silicon film. No dislocations are required for the process, making it a promising approach for achieving high-quality strained-silicon for device applications. To prevent the diffusion of boron and phosphorus into the silicon from the BPSG, a thin nitride film was inserted between the bi-layer and BPSG to act as a diffusion barrier, so that a lightly doped, sub-10-nm s-SOI layer (0.73% strain) was demonstrated. N-channel MOSFETs fabricated in a 25-nm silicon layer with 0.6% strain showed a mobility enhancement of 50%.
TL;DR: In this article, a closed oxide layer, containing nearly exclusively only titanium and oxygen, was formed with the nickel anti-segregating towards the bulk into a Ni 3 Ti layer.
Abstract: Super-elastic Nitinol (NiTi alloys) possesses superior mechanical properties compared to conventional titanium alloys, which—together with a shape memory effect—should predestine them for modern applications However, a biocompatibility below the excellent values of titanium, coupled with the lurking shadow of nickel outdiffusion presently precludes a widespread use in biomedical applications It is shown that oxygen ion implantation, especially using plasma immersion ion implantation for three-dimensional objects, is a highly satisfactory method to obtain both objectives SE 508 substrates were implanted at elevated temperatures with oxygen Subsequently, the films were investigated using elastic recoil detection analysis (ERDA) and X-ray diffraction (XRD) A closed oxide layer, containing nearly exclusively only titanium and oxygen, was formed with the nickel anti-segregating towards the bulk into a Ni 3 Ti layer Thus, an effective diffusion barrier was formed Higher temperatures than 400 °C lead to thermal diffusion of Ni, increasing the Ni concentration in the near surface region
TL;DR: In this paper, a chemically grown oxide layer was proposed to prevent dopant diffusion between semiconductor layers, which may be formed within active devices such as diodes or bipolar transistors.
Abstract: The invention is a chemically grown oxide layer which prevents dopant diffusion between semiconductor layers. The chemically grown oxide layer may be so thin that it does not form a barrier to electrical conduction, and thus may be formed within active devices such as diodes or bipolar transistors. Such a chemically grown oxide film is advantageously used to prevent dopant diffusion in a vertically oriented polysilicon diode formed in a monolithic three dimensional memory array.
TL;DR: In this paper, a method for forming a ruthenium metal layer is described, where the patterned substrate contains one or more vias or trenches, or combinations thereof.
Abstract: A method for forming a ruthenium metal layer includes providing a patterned substrate in a process chamber of a deposition system, where the patterned substrate contains one or more vias or trenches, or combinations thereof, depositing a first ruthenium metal layer on the substrate in an atomic layer deposition process, and depositing a second ruthenium metal layer on the first ruthenium metal layer in a thermal chemical vapor deposition process. The deposited ruthenium metal layer can be used as a diffusion barrier layer, a seed layer for electroplating, or both.
TL;DR: In this article, improved electrochemical biosensor strips and methods for determining the concentration of an analyte in a sample were presented. But the present method is limited to the detection of red blood cells and manufacturing variances.
Abstract: The present invention relates to improved electrochemical biosensor strips and methods for determining the concentration of an analyte in a sample. By selectively measuring a measurable species residing in a diffusion barrier layer, to the substantial exclusion of the measurable species residing exterior to the diffusion barrier layer, measurement errors introduced by sample constituents, such as red blood cells, and manufacturing variances may be reduced.