Abstract: ▪ Abstract The transition to copper-based interconnects for sub-quarter-micron device technologies has generated significant challenges in the identification and development of the robust material and process technologies required to form reliable multilevel metallization interconnects. In particular, a critical need exists for the identification and development of diffusion barrier/adhesion promoter liner materials that provide excellent performance in preventing the diffusion and intermixing of copper with the adjacent dielectric and semiconductor regions of the computer chip. This review summarizes key technology trends in interconnect metallization, with emphasis on ultrathin liner materials, predominant diffusion mechanisms in liner materials, and most promising candidate liners for copper metallization. Key results are presented from the development of physical vapor deposition and chemical vapor deposition processes for binary refractory metal nitrides, such as tantalum nitride and tungsten nitride...

Abstract: A diffusion barrier for an implantable device, such as a stent, carrying a therapeutic or bioactive substance is disclosed. The diffusion barrier reduces the rate at which the therapeutic or bioactive substance is released from the device. The diffusion barrier can be made from a polymeric material impregnated with particles.

Abstract: The reaction mechanisms in the Si/Ta/Cu metallization system and their relation to the microstructure of thin films are discussed on the basis of experimental results and the assessment of the ternary Si–Ta–Cu phase diagram at 700 °C. With the help of sheet resistance measurements, Rutherford backscattering spectroscopy, x-ray diffraction, a scanning electron microscope, and a transmission electron microscope, the Ta barrier layer was observed to fail at temperatures above 650 °C due to the formation of TaSi2, the diffusion of Cu through the silicide layer, and the resulting formation of Cu3Si precipitates. However, in order for the TaSi2 phase to form first, the Ta diffusion barrier layer must be thick enough (e.g., 50–100 nm) to prevent Cu diffusion into the Si substrate up to the temperature of TaSi2 formation (∼650 °C). Independent of the Ta layer thickness, Cu3Si was present as large nodules, whereas the TaSi2 existed as a uniform layer. The resulting reaction structure was found to be in local equilibrium on the basis of the assessed Si–Ta–Cu phase diagram at 700 °C, and therefore no further reactions were expected. The role of oxygen was also found to be important in the reactions and it seems to have a strong effect on the thermal stability of the barrier layer.

Abstract: The requirement for improved electrical performance and reduced silicon area has driven Copper to replace Aluminum interconnection as silicon technology is scaled beyond 0.25 /spl mu/m. The front-end change, in turn, pushes wirebond pad pitch from above 100 /spl mu/m to 80 /spl mu/m-66 /spl mu/m range. This creates challenges for back-end to probe and wire bond at fine pitch geometry onto a readily oxidized Copper surface. After several re-metallization structures and types of metallurgy were evaluated, capping Copper bond pads with Aluminum was selected as the primary approach for probing and wirebonding Copper devices. Aluminum re-metallization structure offers many advantages that help leverage existing tooling and knowledge in fab, probing and wire bonding processes. This paper will describe probe and wirebond experiments used to select the proper adhesion and diffusion barrier between Copper and Aluminum, and Aluminum thickness that can withstand the mechanical stress during probing and wire bonding. Probe mark depth and the impact of probe marks to the underlying barrier and Copper pad were examined. Ball shear, wire rip and corresponding failure modes, intermetallic coverage and cratering analysis were evaluated at various readpoints of thermal aging study to evaluate the integrity of the re-metallization structure as well as the quality of ball bonds onto the new structure. Contact resistance measurement and reliability assessment were also performed. One re-metallization structure was recommended for Copper High Performance wire bonded devices.

Abstract: The interaction between copper interconnects and low-k hydrogen silsesquioxane (HSQ) film was investigated using a Cu/HSQ/Si metal insulation semiconductor capacitor and NH/sub 3/ plasma post-treatment. Owing to serious diffusion of copper atoms in HSQ film, degradations of the dielectric properties are significant with the increase of thermal stress. The leakage current behavior in high field conduction is well explained by the Poole-Frenkel (P-F) mechanism. By applying NH/sub 3/-plasma treatment to the HSQ film, however, the leakage current is decreased and P-F conduction can be significantly suppressed. In addition, the phenomenon of serious Cu penetration is not observed by means of electrical characteristic measurements and secondary ion mass spectroscopy (SIMS) analysis even in the absence of diffusion barrier layers. This indicates the copper diffusion in low-k HSQ film can he effectively blocked by NH/sub 3/ plasma post-treatment.

Abstract: A thermally stable Cu/ZrN/Si contact system using a ZrN diffusion barrier of low resistivity was developed. In the contact system, the growth of an oriented ZrN(100) layer on Si(100), and subsequent growth of a Cu(110) layer on ZrN(100) were observed. The obtained contact system was fairly stable after annealing even at 750 °C for 1 h without any diffusion and/or reactions at either the interface of Cu/ZrN or ZrN/Si. It was revealed that the ZrN layer with low electrical resistivity showed a high performance as a diffusion barrier, and was one of the excellent materials for the use in ultralarge scale integration technology.

Abstract: Tantalum-related thin films containing different amounts of nitrogen are sputter deposited at different argon-to-nitrogen flow rate ratios on (100) silicon substrates Using x-ray diffractometry, transmission electron microscopy, composition and resistivity analyses, and bending-beam stress measurement technique, this work examines the impact of varying the nitrogen flow rate, particularly on the crystal structure, composition, resistivity, and residual intrinsic stress of the deposited Ta2N thin films With an adequate amount of controlled, reactive nitrogen in the sputtering gas, thin films of the tantalum nitride of nominal formula Ta2N are predominantly amorphous and can exist over a range of nitrogen concentrations slightly deviated from stoichiometry The single-layered quasi-amorphous Ta2N (a-Ta2N) thin films yield intrinsic compressive stresses in the range 3–5 GPa In addition, the use of the 40-nm-thick a-Ta2N thin films with different nitrogen atomic concentrations (33% and 36%) and layering designs as diffusion barriers between silicon and copper are also evaluated When subjected to high-temperature annealing, the single-layered a-Ta2N barrier layers degrade primarily by an amorphous-to-crystalline transition of the barrier layers Crystallization of the single-layered stoichiometric a-Ta2N (Ta67N33) diffusion barriers occurs at temperatures as low as 450 °C Doing so allows copper to preferentially penetrate through the grain boundaries or thermal-induced microcracks of the crystallized barriers and react with silicon, sequentially forming {111}-facetted pyramidal Cu3Si precipitates and TaSi2 Overdoping nitrogen into the amorphous matrix can dramatically increase the crystallization temperature to 600 °C This temperature increase slows down the inward diffusion of copper and delays the formation of both silicides The nitrogen overdoped Ta2N (Ta64N36) diffusion barriers can thus be significantly enhanced so as to yield a failure temperature 100 °C greater than that of the Ta67N33 diffusion barriers Moreover, multilayered films, formed by alternately stacking the Ta67N33 and Ta64N36 layers with an optimized bilayer thickness (λ) of 10 nm, can dramatically reduce the intrinsic compressive stress to only 07 GPa and undergo high-temperature annealing without crystallization Therefore, the Ta67N33/Ta64N36 multilayered films exhibit a much better barrier performance than the highly crystallization-resistant Ta64N36 single-layered films

Abstract: A method for preparing a copper pad surface for electrical connection that has superior diffusion barrier and adhesion properties is provided. In the method, a copper pad surface is first provided that has been cleaned by an acid solution, a protection layer of a phosphorus or boron-containing metal alloy is then deposited on the copper pad surface, and then an adhesion layer of a noble metal is deposited on top of the protection layer. The protection layer may be a single layer, or two or more layers intimately joined together formed of a phosphorus or boron-containing metal alloy such as Ni-P, Co-P, Co-W-P, Co-Sn-P, Ni-W-P, Co-B, Ni-B, Co-Sn-B, Co-W-B and Ni-W-B to a thickness between about 1,000 Å and about 10,000 Å. The adhesion layer can be formed of a noble metal such as Au, Pt, Pd and Ag to a thickness between about 500 Å and about 4,000 Å.

Abstract: A silicon carbon nitride (SiCN) layer is provided which has a low leakage current and is effective in preventing the migration or diffusion of metal or copper atoms through the SiCN layer. The SiCN layer can be used as a diffusion barrier between a metal portion (such as a copper line or via) and an insulating dielectric to prevent metal atom diffusion into the dielectric. The SiCN layer can also be used as an etchstop or passivation layer. The SiCN layer can be applied in a variety ways, including PECVD (e.g., using SiH 4 , CH 4 , and NH 3 ) and HDP CVD (e.g., using SiH 4 , C 2 H 2 , and N 2 ).

Abstract: A damascene interconnect containing a dual etch stop/diffusion barrier. The conductive material of the damascene interconnect is capped with a conductive metal diffusion barrier cap, typically using electroless deposition, and, optionally, with a dielectric etch-stop layer. An optional chemical mechanical polish-stop layer may also be present. The different methods of the invention allow the CMP stop, reactive-ion etch stop, and metal diffusion barrier requirements of the different layers to be decoupled. A preferred conductive material is copper.

Abstract: This invention relates to a robust method of fabrication used for semiconductor integrated circuit devices, and more specifically to the formation of an improved copper metal diffusion barrier layer, TiSiN, by a combination of metal-organic chemical vapor deposition (MOCVD) and multi-step plasma treatment that improves the diffusion resistant properties of the barrier layer (at both interfaces or surfaces) for both copper and silicon diffusion, in a single and dual damascene process, to fabricate reliable metal interconnects and contact vias. After a metal-organic chemical vapor deposition (MOCVD) to form TiN x C y O z , TiC x N y H z complexes, a multi-step plasma treatment follows. The first plasma treatment bombards the surface with nitrogen and hydrogen ions to reduce the complexes to TiN. The TiN barrier layer is then treated with an enhanced plasma deposition by using silane and bombarding the surface with silicon ions. The net result is the formation of a TiSiN film with improved diffusion resistance.

Abstract: A multilayer interconnected electronic component having increased electromigration lifetime is provided. The interconnections are in the form of studs and comprise vertical side walls having a refractory metal diffusion barrier liner along the sidewalls. The stud does not have a barrier layer at the base thereof and the base of the stud contacts the metallization on the dielectric layer of the component. An adhesion layer can be provided between the base of the stud and the surface of the metallization and the adhesion layer may be continuous or discontinuous. The adhesion layer is preferably a metal such as aluminum which dissolves in the stud or metallization upon heating of the component during fabrication or otherwise during use of the component. A preferred component utilizes a dual Damascene structure.

Abstract: A method of forming an oxidation diffusion barrier stack for use in fabrication of integrated circuits includes forming an inorganic antireflective material layer on a semiconductor substrate assembly with an oxidation diffusion barrier layer then formed on the inorganic antireflective material layer. Another method of forming such a stack includes forming a pad oxide layer on the semiconductor substrate assembly with an inorganic antireflective material layer then formed on the pad oxide layer and an oxidation diffusion barrier layer formed on the antireflective material layer. Another method of forming the stack includes forming a pad oxide layer on the semiconductor substrate assembly. A first oxidation diffusion barrier layer is then formed on the pad oxide layer, an inorganic antireflective material layer is formed on the first oxidation diffusion barrier layer, and a second oxidation diffusion barrier layer is formed on the inorganic antireflective material layer. The antireflective material layer may include a layer of material selected from the group of silicon nitride, silicon oxide, and silicon oxynitride and further may be a silicon-rich layer. The oxidation diffusion barrier stacks may be used for oxidation of field regions for isolation in an integration circuit. Further, the various oxidation diffusion barrier stacks are also described.

Abstract: Diffusion barrier characteristics and electrical properties of self-aligned MgO layers obtained from a Cu(Mg) alloy film have been investigated. Self-aligned surface and interfacial MgO layers were formed upon annealing a Cu(Mg) film in an oxygen ambient and prevented interdiffusion of Cu in SiO2 up to 700 °C. The thermal stability of a pure Cu/TiN/Si multilayer system has been significantly enhanced up to 800 °C by the MgO layers by forming a MgO/Cu/MgO/TiN/Si multilayer system. A combined structure of Si3N4(500 A)/MgO(100 A) increased the breakdown voltage up to 20 V from 15 V and reduced the leakage current density down to 3×10−9 A/cm2 from 1×10−8 A/cm2 compared to a pure copper system. Consequently, the deposition of Cu(Mg) alloy followed by annealing in an oxygen ambient gives rise to the formation of a self-aligned MgO layer with excellent diffusion barrier and electrical characteristics and the film can be applied as a gate electrode in thin-film transistor/liquid-crystal displays, resulting in a r...

Abstract: A structure (2) comprises a crystalline textured silicon thin film (5) over a biaxially textured lattice-matched diffusion barrier buffer layer (4) on a thermal expansion-matched inert substrate (3). In the structure (2): (a) the substrate (3) consists of a material which has a thermal expansion coefficient of not more than 3 times that of the silicon material, has a structure not affecting the buffer layer texture and is chemically and mechanically resistant to buffer layer and silicon layer deposition; and (b) the buffer layer (4) has a biaxial texture with one crystal axis perpendicular to the substrate surface, forms a diffusion barrier between the silicon layer and the substrate and exhibits lattice structure and lattice constant matching with the silicon layer material. An Independent claim is also included for production of the above structure. Preferred Features: The substrate consists of a glass or a preferably nickel -based metallic material.

Abstract: In accordance with one embodiment of the invention, a diffusion barrier layer is formed in a copper interconnect structure by first forming a layer of intermetal dielectric material on an underlying layer of conductive material. A pattern of dual damascene structures is then formed in the interconnect dielectric layer. An adhesion layer is then formed on exposed sidewalls of the damascene structure and on the upper surface of the intermetal dielectric material. The adhesion-layer-lined dual damascene structures are then filled with a conductive material that includes copper. The copper-including conductive material is then planarized to the upper surface of the intermetal dielectric material. Intermetal dielectric material is then removed to expose the conductive material. A diffusion barrier material is then deposited on exposed surfaces of the conductive material. Low k dielectric material is then disposed over the entire interconnect structure to fill the gaps, thus providing a low k solution and structural integrity to the interconnect.

Abstract: A method of forming conducting diffusion barriers is provided The method produces substantially amorphous conducting diffusion barriers by depositing materials with varying ratios of elements throughout the diffusion barrier Diffusion barriers of metal nitride, metal silicon nitride, are deposited using CVD, PECVD, or ALCVD, by depositing material with a first ratio of elements and then depositing substantially identical material with a different ratio of elements The actual elements used are the same, but the ratio is changed By changing the ratio of the elements within the same diffusion barrier, density variations are produced, and the material is not able to form undesirable polycrystalline structures

Abstract: Copper metallization for GaAs was evaluated by using Cu/Ta/GaAs multilayers for its thermal stability. A thin Ta layer of 40 nm was sputtered on the GaAs substrate as the diffusion barrier before copper film metallization. As judged from sheet resistance, x-ray diffraction, Auger electron spectroscopy and transmission electron microscopy, the Cu/Ta films with GaAs were very stable up to 500 °C without migration into GaAs. After 550 °C annealing, the interfacial mixing of Ta with GaAs substrate occurred, resulting in the formation of TaAs2. At 600 °C annealing, the reaction GaAs with Ta and Cu formed TaAs, TaAs2, and Cu3Ga, resulting from Cu migration and interfacial instability.

Abstract: Cobalt silicide formation has been studied in the presence of a thin, chemically grown interfacial SiO2 and a Ti capping layer. It is found that for ex situ annealing without a capping layer (Co/SiO2/Si system), no silicide is formed. In the presence of a Ti capping layer (Ti/Co/SiO2/Si system), CoSi is formed, followed by CoSi2 at higher temperature. The CoSi formation temperature is dependent on the capping layer thickness. The reaction mechanism has been studied in detail. It is found that the function of the Ti capping layer is twofold: first of all the capping layer protects the silicidation reaction from oxygen contamination. Second, Ti from the cap is able to diffuse through the unreacted Co and to transform the interfacial SiO2 diffusion barrier into a CoxTiyOz diffusion membrane. The CoSi2 layer has a preferential epitaxial orientation with the (100) silicon substrate. The epitaxial quality is dependent on the annealing temperature and the thickness of the Co and Ti layers. It is shown that CoSi2 layers formed from a Ti/Co/SiO2/Si system have a better thermal stability and more ideal electrical characteristics than the polycrystalline CoSi2 formed in the standard Co/Si reaction.

Abstract: A barrier layer is formed over the substrate by deposition, and a first dielectric is formed over the diffusion barrier layer by deposition. A etching stop layer and a second dielectric are formed in turn over the first dielectric by deposition. Next, a hard mask is formed on the second dielectric. Then, a photoresist layer is formed over the hard mask, and defining the photoresist layer. And then dry etching is carried out by means of the photoresist layer as the mask to form a via hole. A gap-filling material is filled on the second dielectric and into the via hole by conventional partial-cured (or un-cured) spin-on glass method. A anti-reflection layer is formed over the second dielectric by deposition. Another photoresist layer is formed on the anti-reflection coating and defined the photoresist layer, and to expose the partial surface of the via hole and the anti-reflection coating. Dry etching is proceed by means of the photoresist layer as a mask, and etching stop layer is as a etching terminal point to remove exposed partial surface of the bottom anti-reflection coating so as to form a trench. Then, the gap-filling material is removed by wet etching. Then a barrier layer is formed, and the seed layer is deposition on the barrier layer, and forming a conduct electricity metal layer on the seed layer. And then, the barrier layer and the anti-reflection coating are removed. Final, a barrier layer is deposition again.

Abstract: A reliable Ir diffusion barrier was prepared on polysilicon plugged substrate with a contact size of 0.6 μm. Using a Ti adhesion layer and stress-relief process, it was possible to integrate the Ir barrier into a high density 4 Mb ferroelectric random access memory device. After heat treating sol-gel derived Pb(Zr1−xTix)O3 (PZT) films at 700 °C, the Ir barrier contact displayed an ohmic behavior and showed a low resistance of 130 Ω per contact in 1k serial contact array. The PZT films on Pt/IrO2/Ir poly-plugged substrate exhibited excellent ferroelectric properties such as remnant polarization and coercive voltage of 25 μC/cm2 and 1.15 V, respectively. Auger depth profile and transmission electron microscopy analyses confirmed that no appreciable oxidation was formed between the Ir barrier and the polysilicon plug.

Abstract: TiB 2 films co-sputtered from boron and TiB 2 targets were used as diffusion barriers between Cu thin films and Si substrates. Material characteristics of TiB 2 films and metallurgical reactions of CuTiB 2 / system annealed in the temperature range 400-800°C for 30 min were investigated by glancing angle X-ray diffraction, Auger electron spectroscopy, X-ray photoelectron spectroscopy, scanning electron microscopy, and sheet resistance measurements, The chemical composition and resistivity of the co-sputtered Ti-B films are sensitive to the bias applied on the substrate. A nanocrystalline TiB 2 film with a resistivity of 300 μΩ cm was obtained when a negative bias of 200 V was applied to the substrate during sputtering. After depositing a copper overlayer, we observed that the sheet resistance of the Cu( 180 nm)/TiB 2 (60 nm)/ system stayed at a constant value after annealing up to 600°C for 30 min; however, the sheet resistance increased by almost five orders of magnitude after annealing at 700 and 800°C. At that point. the surface morphology was seriously deteriorated and formation of Cu 3 Si was also observed. The co-sputtered TiB 2 diffusion barrier accordingly breaks down after annealing at 700°C for 30 min.

Abstract: One major concern of conservators and archaeologists is to limit the alteration and the corrosion of metallic archaeological objects. Organic coatings are one of the most important ways of protecting metal against corrosive agents, thanks to their diffusion barrier properties. The aim of this work was to develop effective protective coatings fitting with the specific requirements of heritage preservation (in particular the questions of reversibility and aesthetic appearance). Ultrathin (5-50 nm) polymer-like films have been deposited by plasma polymerisation in a methane or propane discharge on various metallic samples (stainless steel, Fe, Cu, Ag and Roman iron nails). Some important results are: 1. on tested substrates, except Ag, adhesion is very good; 2. concerning the reversibility of such layers, they can be totally removed in H 2 plasma; 3. the coatings are slightly coloured, which seems linked to the amount of unsaturated CC bonds in the C layer and to a finite electrical conductivity; 4. they show interesting barrier diffusion properties to H 2 S, O 2 and water vapour molecules; and 5. on silver substrates, some problems of adhesion are observed due to the diffusion of Ag ions through the organic films.

Abstract: Provided is a semiconductor memory device in which defective contact, deterioration in transistor characteristics and other problems are solved with a thermally stable, conductive diffusion barrier layer against oxygen, and against constituent elements in a plug material and a lower electrode, formed at the interface between a plug and the lower electrode made of a noble metal. The semiconductor memory device comprises a dielectric capacitor of a stacked structure including a first electrode (a lower electrode), a dielectric film and a second electrode (an upper electrode) and a conductive plug connected to the lower electrode, wherein the lower electrode connected to the conductive plug includes a metal suboxide layer with conductiveness and a diffusion barrier layer blocking diffusion of oxygen, and the metal suboxide layer and the diffusion barrier layer are stacked in the order from the conductive plug side of the lower electrode.