Abstract: Tantalum and titanium source reagents are described, including tantalum amide and tantalum silicon nitride precursors for the deposition of tantalum nitride material on a substrate by processes such as chemical vapor deposition, assisted chemical vapor deposition, ion implantation, molecular beam epitaxy and rapid thermal processing. The precursors may be employed to form diffusion barrier layers on microelectronic device structures enabling the use of copper metallization and ferroelectric thin films in device construction.

Abstract: Diffusion barrier properties of very thin sputtered Ta and reactively sputtered TaN films used as a barrier layer between Cu and Si substrates were investigated using electrical measurement and materials analysis. The Cu/Ta/p + -n junction diodes with the Ta barrier of 5, 10, and 25 nm thicknesses were able to sustain a 30 min thermal annealing at temperatures up to 450, 500, and 550°C, respectively, without causing degradation to the device's electrical characteristics. The barrier capability of Ta layer can be effectively improved by incorporation of nitrogen in the Ta film using reactive sputtering technique. For the Cu/TaN/p + -n junction diodes with the TaN barrier of 5, 10, and 25 nm thicknesses, thermal stability was able to reach 500, 600, and 700°C, respectively. We found that failure of the very thin Ta and TaN barriers was not related to Ta silicidation at the barrier/Si interface. Failure of the barrier layer is presumably due to Cu diffusion through the barrier layer during the process of thermal annealing via local defects, such as grain boundaries and stress-induced weak points.

Abstract: Electrolessly deposited materials were investigated as possible diffusion barrier layers for multilayer microelectronic structures. Attention was focused on selective deposition of barrier layers on various surfaces, the barrier's capability to inhibit Cu diffusion, changes in Cu resistivity caused by barrier material diffusion into Cu, and adhesion between a polyimide film and the barrier layer. Electroless Co(P) was the most effective barrier to Cu diffusion at elevated temperature, even at Co(P) thicknesses as low as 500 A. Diffusion-barrier effectiveness of electrolessly deposited materials decreased in the following order: Co(P) > Ni-Co(P) ≃ Ni(P) > pure metals Co, Ni). Although a polyimide film bonded strongly to electrolessly deposited Ni(P) layers and only weakly to as-deposited Co(P), electroless Ni(P) significantly increased the Cu resistivity through interdiffusion. Polyimide adhesion to Co(P) was improved by oxidizing a Co(P) surface immediately after deposition to grow a passive film 50-75 A thick, yielding a surface to which the polyimide adheres strongly and reproducibly. A low-energy-beam, scanning electron microscopy/energy-dispersive X-ray analysis technique (SEM/EDX) was developed to measure the nonoxidized thin Co(P) barrier layer thickness.

Abstract: Improved methods for filling openings in silicon substrates with copper and the metal interconnects so produced are provided. One method involves the use of a Ti x Al y N z barrier layer which is stable to the high temperatures required to reflow copper after PVD deposition. Another method involves the use of an aluminum wetting layer between a barrier layer and the copper which effectively lowers the temperature at which copper reflows and therefore allows the use of typical barrier layers.

Abstract: A method for use in the fabrication of integrated circuits includes providing a substrate assembly having a surface and forming a barrier layer over at least a portion of the surface. The barrier layer is formed of a platinum(x):ruthenium(1−x) alloy, where x is in the range of about 0.60 to about 0.995; preferably, x is in the range of about 0.90 to about 0.98. The barrier layer may be formed by chemical vapor deposition and the portion of the surface upon which the barrier layer is formed may be a silicon containing surface. The method is used in formation of capacitors, storage cells, contact liners, etc.

Abstract: An interconnect line on an IMD layer on a semiconductor device is formed in an interconnect hole in the IMD layer. The interconnect hole has walls and a bottom in the IMD layer. A diffusion barrier is formed on the walls and the bottom of the hole. Fill the interconnect hole with a copper metal line. Perform a CMP step to planarize the device and to remove copper above the IMD layer. Deposit a passivating metal layer on the surface of the copper metal line encapsulating the copper metal line at the top of the hole. Alternatively, a blanket deposit of a copper metal line layer covers the diffusion layer and fills the interconnect hole with a copper metal line. Perform a CMP process to planarize the device to remove copper above the IMD layer. Deposit a passivating metal layer on the surface of the copper metal line encapsulating the copper metal line at the top of the hole in a self-aligned deposition process.

Abstract: Adhesion of a copper film, such as a copper interconnect (24), to a substrate underlayer, such as a substrate diffusion barrier, is enhanced with adhesion promotion techniques. The adhesion promotion techniques can repair the interface (26) of the copper film and the substrate to enhance adhesion of the copper film for high-yield formation of inlaid copper metal lines and plugs. For instance, thermal annealing of a seed layer, including a copper seed layer, an alloy seed layer or a reactant seed layer, can repair contamination at the interface of the seed layer and the substrate. Alternatively, the adhesion promotion techniques can avoid contamination of the interface by depositing an inert seed layer, such as a noble (e.g., platinum) or passivated metal seed layer, or by depositing the seed layer under predetermined conditions that minimize contamination of the interface, and then depositing a bulk coper layer under predetermined conditions that maximize throughput. Alternatively, the adhesion promotion techniques can avoid the formation of an interface by graduated deposition of a first material and copper.

Abstract: A new type of miniature amperometric oxygen sensor has been developed. The sensors are high temperature micro-electrochemical devices that use a dense diffusion barrier of a metal oxide that readily transports oxygen and conduct electrons. The diffusion barrier is deposited in thin film form on top of a zirconia-based electrochemical pump. When a voltage is applied to the pump, oxygen is depleted from one side of the diffusion barrier and the ionic current is proportional to the flux of oxygen across the thin film layer. If the pumping voltage reaches a high enough value, the transport of oxygen across the membrane and hence the device’s output current, will be limited by the external, oxygen concentration and the transport characteristics of the diffusion barrier. The sensors can be manufactured in a planar design that offers a faster time response, much simpler design and potentially lower cost than existing limiting current oxygen sensors.

Abstract: The use of Al–O–N films as a diffusion barrier for components with a high thermal load, e.g. in gas turbines, was investigated. Therefore, films with compositions along the quasibinary section Al 2 O 3 –AlN were deposited onto Ni base superalloy (CMSX4) substrates by means of magnetron sputtering ion plating (MSIP) at 373 K substrate temperature and characterized with regard to their composition and structure using X-ray photoelectron spectroscopy (XPS) and grazing incidence X-ray diffraction (XRD). The phase stability of the films was examined by annealing under inert atmosphere at temperatures up to 1473 K for 4 h and subsequent XRD analyses. To investigate a possible application of these films as a diffusion barrier between Ni base superalloys and MCrAlY, the latter in technical applications serving as corrosion protection for superalloys, a MCrAlY coating was deposited onto selected samples. Without a diffusion barrier and operating temperatures of and above 1373 K, noticeable interdiffusion could be observed. After annealing the CMSX4–Al–O–N–MCrAlY composites for 4 h the interfaces CMSX4–Al–O–N and Al–O–N–MCrAlY were investigated by XRD and energy-dispersive X-ray spectroscopy (EDX). The analyses showed that ternary Al–O–N films were grown in X-ray amorphous structure and remained in that state after annealing the CMSX4–Al–O–N–MCrAlY composites for 4 h at 1373 K. Al 2 O 3 was also deposited in X-ray amorphous structure, but converted into α-Al 2 O 3 after annealing. In the case of the Al 2 O 3 , interdiffusion between CMSX4 and MCrAlY was observed during annealing, especially evident regarding titanium. In contrast to this, ternary Al–O–N films showed a better performance as a diffusion barrier, e.g. no titanium was detectible in the Al–O–N or MCrAlY film. A possible explanation is that the ternary films remained in their amorphous structure, whereas Al 2 O 3 , which at the low substrate temperature supposedly was deposited nanocrystalline in the cubic γ-Al 2 O 3 structure, converted into the hexagonal α-modification during annealing. This transition is assumed to be responsible for the permeability for interdiffusing elements.

Abstract: A method is disclosed for forming copper damascene interconnects without the attendant CMP (chemical-mechanical polishing) dishing problem that is encountered in the art. This is accomplished by first lining the inside walls of a dual damascene structure with a diffusion barrier layer, and then depositing copper metal into the damascene structure. Secondly, as a key aspect of the invention, and before removing the excess copper either by conventional etching techniques-which is difficult for copper- or by conventional CMP- which causes dishing in grooves or trenches- an etch stop layer is deposited covering the copper layer. Portions of the etch stop layer is next removed from the high regions of the underlying copper by a quick first CMP so that other portions of the etch stop layer over the wider trenches/groove remain low and unaffected. The high regions now exposed are etched while the low regions protected by the etch-stop layer still remain unaffected. When the copper etching reaches a level below the level of the low regions, a global CMP is performed so that all of the excess copper is removed and the level of the copper especially over the wider trench areas reaches within very close proximity of the level of the insulation layer surrounding the copper damascene- and without dishing.

Abstract: A method of forming a dielectric layer includes, a) chemical vapor depositing a dielectric layer of Ta 2 O 5 atop a substrate; and b) providing a predominately amorphous diffusion barrier layer over the Ta 2 O 5 dielectric layer. A method of forming a capacitor includes, a) providing a node to which electrical connection to a capacitor is to be made; b) providing a first electrically conductive capacitor plate over the node; c) chemical vapor depositing a capacitor dielectric layer of Ta 2 O 5 over the first electrically conductive capacitor plate; and d) providing a predominately amorphous diffusion barrier layer over the Ta 2 O 5 dielectric layer. A capacitor construction is also disclosed. The preferred amorphous diffusion barrier layer is electrically conductive and constitutes a metal organic chemical vapor deposited TiC x N y D z , where “x” is in the range of from 0.01 to 0.5, and “y” is in the range of from 0.99 to 0.5, and “z” is in the range of from 0 to 0.3, with the sum of “x”, “y” and “z” equalling about 1.0. Such is preferably deposited by utilizing a gaseous titanium organometallic precursor of the formula Ti(NR 2 ) 4 , where R is selected from the group consisting of H and a carbon containing radical, and utilizing deposition conditions of from 200° C. to 600° C. and from 0.1 to 100 Torr.

Abstract: A capacitor having a pair of conductive electrodes separated by a dielectric layer and wherein at least one of the electrodes comprise Ti x Al 1-x N, and wherein the variable "x" lies in a range of about 04 to about 08 The invention also contemplates a method for forming an electrically conductive diffusion barrier on a silicon substrate and which comprises providing a chemical vapor deposition reactor having a chamber; positioning the silicon substrate in the chemical vapor deposition reactor chamber; providing a source of gaseous titanium aluminum and nitrogen to the chemical vapor deposition reactor chamber; and providing temperature and pressure conditions in the chemical vapor deposition reactor chamber effective to deposit an electrically conductive diffusion barrier layer on the silicon substrate comprising Ti x Al 1-x N, and wherein the variable "x" is in a range of about 04 to about 08

Abstract: The adhesion of a diffusion barrier or capping layer to a Cu or Cu alloy interconnect member is significantly enhanced by treating the exposed surface of the Cu or Cu alloy interconnect member: (a) under plasma conditions with ammonia and silane or dichlorosilane to form a copper silicide layer thereon; or (b) with an ammonia plasma followed by reaction with silane or dichlorosilane to form a copper silicide layer thereon. The diffusion barrier layer is then deposited on the copper silicide layer. Embodiments include electroplating or electroless plating Cu or a Cu alloy to fill a damascene opening in a dielectric interlayer, chemical mechanical polishing, then treating the exposed surface of the Cu/Cu alloy interconnect to form the copper silicide layer thereon, and depositing a silicon nitride diffusion barrier layer on the copper silicide layer.

Abstract: Methods of forming integrated circuit capacitors include the steps of forming a lower electrode of a capacitor by forming a conductive layer pattern (e.g., silicon layer) on a semiconductor substrate and then forming a hemispherical grain (HSG) silicon surface layer of first conductivity type on the conductive layer pattern. The inclusion of a HSG silicon surface layer on an outer surface of the conductive layer pattern increases the effective surface area of the lower electrode for a given lateral dimension. The HSG silicon surface layer is also preferably sufficiently doped with first conductivity type dopants (e.g., N-type) to minimize the size of any depletion layer which may be formed in the lower electrode when the capacitor is reverse biased and thereby improve the capacitor's characteristic Cmin/Cmax ratio. A diffusion barrier layer (e.g., silicon nitride) is also formed on the lower electrode and then a dielectric layer is formed on the diffusion barrier layer. The diffusion barrier layer is preferably made of a material of sufficient thickness to prevent reaction between the dielectric layer and the lower electrode and also prevent out-diffusion of dopants from the HSG silicon surface layer to the dielectric layer. The dielectric layer is also preferably formed of a material having high dielectric strength to increase capacitance.

Abstract: An interconnect structure capable of reducing intralevel capacitance in a damascene metalization process employs entrapped air gaps between metal lines. The structure comprises at least first and second metal regions separated by a dielectric region, an air gap formed at least partially within the dielectric region, a diffusion barrier positioned over the two metal regions covering a portion of the upper surface of the air gap, and an insulating layer positioned over the diffusion barrier sealing the upper surface of the air gap.

Abstract: A platinum film, which is used as a bottom electrode for a capacitor in a DRAM cell or a non-volatile ferroelectric memory cell, is formed in two separate processes, wherein a first thickness platinum part thereof is deposited under an inert gas atmosphere, and the second thickness platinum part is deposited under an atmosphere containing oxygen, nitrogen and/or a mixture thereof as well as an inert gas. The platinum film is annealed under a vacuum atmosphere to remove the oxygen an/or nitrogen introduced during the deposition of the second thickness platinum part. The annealed platinum film prevents formation of an oxide on a functional intermediate film such as a diffusion barrier layer or an adhesion layer, which is provided below the bottom electrode of platinum film.

Abstract: An integrated circuit fabrication method for filling a high-aspect-ratio via with a metallization layer wherein there is provided a dielectric layer having a via therein. A wetting layer is deposited over the dielectric layer and within the via and the via sidewalls, the wetting layer being of a material which lowers the melting temperature of the metallization when combined with the metallization. The metallization layer is deposited over the wetting layer and the via but not completely filling the via with the metallization. The wetting agent with metallization thereon are heated to a temperature below the melting temperature of the metallization, the temperature being sufficient to cause the wetting layer to combine with the metallization, lower the melting temperature of the metallization to the temperature or below the heating temperature to cause the metallization to flow and fill the via. A diffusion barrier layer can be provided on the wetting layer over horizontal portions of the dielectric layer, but not on the wetting layer at sidewalls of the via.