Abstract: The corrosion behavior of copper in aqueous solutions of different pH values was investigated using electrochemical and surface analysis methods. It was shown that the corrosion mechanism changed with pH and was associated with morphology of the surf ace films formed. In solution of pH 3, the copper surface was covered with porous corrosion products of cuprous oxide (Cu2O). Corrosion was controlled predominately by diffusion in solution. In solutions of pH 4 to pH 5, formation of cubic Cu2O on the copper surface provided a diffusion barrier to copper dissolution. The anodic process was controlled by a mixed diffusion of copper ions in oxide films and in solution. In solutions of pH 6 to pH 9, the oxide films (Cu2O) became more protective. Diffusion in the oxide films became a rate-determining step of anodic dissolution. In pH 10 solution, a thin, compact Cu2O film formed, and spontaneous passivation was observed. At pH 12 and pH 13, analysis by x-ray photoelectron spectroscopy (XPS) and scanning ...

Abstract: The actual mechanism involved in Au-Si wafer bonding is controversial. Usually a titanium or chromium layer is deposited in between the (oxidized) silicon substrate and the gold layer to ensure adhesion. The resulting bond of two such wafers after annealing is generally considered to be eutectic, however, the bond temperature required is higher than would be expected from the Au-Si eutectic temperature. Moreover, silicide grains are formed at the bonding interface. In this paper it is proposed that the actual bonding is initiated by the dissolution of the oxide layer by silicidation of the titanium adhesion/barrier layer. The subsequent direct Au-Si contact enables the formation of the euteetic phase. The silicidation is required to obtain the eutectic alloy with 19 at.% Si despite the Ti diffusion barrier. The bonding temperature required is, therefore, set by the silicidation process rather than by the eutectic phase. Several experiments have been designed to support this theory. AI-Si eutectic bonding has been investigated, as it is not complicated by an adhesion metal and experiments demonstrate reliable bonding close to its eutectic temperature. Moreover, a Ti/Au/Si/Au stack has been fabricated to be used as a eutectic solder, giving bonding at a temperature not affected by silicidation. Keywords Eutectic bonding Gold Silicide bonding Silicon Wafer bonding

Abstract: Disclosed is an improved process and liner for trench isolation which includes either a single oxynitride layer or a dual oxynitride (or oxide)/nitride layer. Such a process and liner has an improved process window as well as being an effective O 2 diffusion barrier and resistant to hot phosphoric and hydrofluoric acids.

Abstract: A copper diffusion barrier is formed on the side walls of vias connected to copper conductors to prevent copper diffusion into inter-level dielectric. A thin film of copper diffusion barrier material is deposited on the wafer post via etch. A sputter etch is performed to remove barrier material from the base of via and to remove copper oxide from the copper conductor. The barrier material is not removed from the sidewall during the sputter etch. Thus, a barrier to re-deposited copper is formed on the via sidewalls to prevent copper poisoning of the dielectric.

Abstract: A wiring structure of a semiconductor device buries an aperture, for example, a contact hole or via hole. The wiring structure includes a semiconductor substrate, an insulating layer formed on the semiconductor substrate and having an aperture formed therein, a diffusion barrier film formed on the inner sidewalls of the aperture and which has a smooth surface without having grain boundaries made of a refractory metal or refractory metal compound, and a metal layer formed on the diffusion barrier film. The metal layer formed on the smooth sidewalls of the diffusion barrier film is made of a uniformly and continuously formed aluminum film having an excellent step coverage. Accordingly, the method for forming the wiring structure effectively buries a contact hole having a high aspect ratio and enhances the reliability of a manufactured device.

Abstract: A method of forming a diffusion barrier on an article of a polymer blend of (i) a high surface energy polymer and (ii) a low surface energy polymer. Most commonly the low surface energy polymer is an organosilicon polymer, as a polysilane or a polysiloxane. The surface of the article is exposed to ozone and ultraviolet radiation to form a diffusion barrier.

Abstract: A dynamic random access memory device ( 100 ) includes storage capacitors using a high dielectric constant material, such as, BaSrTiO 3 , SrBi 2 Ta 2 O 9 and PbZrTiO 3 , for the capacitors' insulator. The device includes a conductive plug ( 106 ) formed over and connecting with a semiconductor substrate ( 102 ). A buffer layer ( 107 ) of titanium silicide lays over the plug, and this layer serves to trap “dangling” bonds and to passivate the underlying surface. A first diffusion barrier layer ( 108 ), e.g., titanium aluminum nitride, covers the titanium silicide. A capacitor first electrode ( 110 ) lays over the diffusion barrier layer. The high dielectric constant material ( 112 ) is laid over the capacitor first electrode. A capacitor second electrode ( 116 ) is laid over the high dielectric constant material. A second diffusion barrier layer ( 120 ) is deposited on the capacitor second electrode. A conductor, such as aluminum ( 130 ), is laid over the second diffusion barrier layer. An isolation dielectric ( 132 ) can be deposited over the conductor at a high temperature without causing oxygen or metallic diffusion through the first and second diffusion barrier layers.

Abstract: Articles for hot hydrocarbon fluid wherein the surface for contacting the fluid is a metal oxide, amorphous glass or metal fluoride diffusion barrier material coated on a metal substrate. The metal oxide, amorphous glass or metal fluoride is deposited by chemical vapor deposition (CVD), e.g., by effusive CVD of an organometallic compound on the surface without the use of carrier gas, without pre-oxidation of the surface and without thermal decomposition of the diffusion barrier coating material. Examples of coating materials deposited by effusive CVD are SiO 2 , TiO 2 , spinel and Al 2 O 3 . The articles having the coated surfaces find utility in components subjected to high temperatures wherein the components are in contact with hydrocarbon fluids without additives, without special attention to quality control and without the need for special processing.

Abstract: We report on a comprehensive study of the growth of 5-nm-thick epitaxial Fe(001) films on Ag(001) substrates which are deposited on Fe-precovered GaAs(001) wafers. We characterize the films in situ by scanning tunneling microscopy, low-energy electron diffraction, X-ray photoelectron spectroscopy, and depth profiling to obtain information about the geometrical and chemical surface structure. We find that the surface morphology is improved by either growing or postannealing the films at elevated temperatures. During deposition at and above room temperature, however, an atomic exchange process is activated that results in a thin Ag film (up to 1 ML) ``floating'' on top of the growing Fe film. We propose and confirm a growth procedure that yields clean, Ag-free surfaces with a morphology superior to the other films. This optimized recipe consists of two steps: (i) low-temperature growth of the first 2 nm in order to form a diffusion barrier for the Ag substrate atoms, and (ii) high-temperature deposition of the final 3 nm to take advantage of the improved homoepitaxial growth quality of Fe at elevated temperatures. The relevance of these results with respect to magnetic properties of multilayers is discussed.

Abstract: Diffusion barrier properties of nanostructured amorphous Ta-Si-N thin films with different N concentrations have been investigated in metallurgical aspects of Cu metallization. When the N content exceeds 40 at. %, the Ta-Si-N film remains in the nanostructure phase even after annealing at 1100 °C for 1 h and effectively prevents Cu diffusion after annealing at 900 °C for 30 min. The reason for the excellent thermal stability is that excess N atoms disturb the grain growth of TaSi2 phase and keep the Ta-Si-N film in the nanostructure phase during the high temperature annealing. The Ta-Si-N film with N content less than 40 at. % fails to prevent the Cu diffusion after annealing at 700 °C for 30 min.

Abstract: A refractory Metal Nitride and a refractory metal Silicon Nitride layer (64) can be formed using metal organic chemical deposition More specifically, tantalum nitride (TaN) (64) can be formed by a Chemical Vapor Deposition (CVD) using Ethyltrikis (Diethylamido) Tantalum (ETDET) and ammonia (NH3) By the inclusion of silane (SiH4), tantalum silicon nitride (TaSiN) (64) layer can also be formed Both of these layers can be formed at wafer temperatures lower than approximately 400° C with relatively small amounts of carbon (C) within the film Therefore, the embodiments of the present invention can be used to form tantalum nitride (TaN) or tantalum silicon nitride (TaSiN) (64) that is relatively conformal and has reasonably good diffusion barrier properties

Abstract: Ti-Si-N films synthesized by reactively sputtering a TiSi2, a Ti5Si3, or a Ti3Si target in Ar/N2 gas mixture were tested as diffusion barriers between planar (100) Si substrates and shallow n+p Si diodes, and Al or Cu overlayers. The stability of the Ti-Si-N barriers generally improves with increasing nitrogen concentration in the films, with the drawback of an increase in the film’s resistivity. Ti34Si23N43 sputtered from the Ti5Si3 target is the most effective diffusion barrier among all the Ti-Si-N films studied. It works as an excellent barrier between Si and Cu. A film about 100 nm thick, with a resistivity of around 700 μΩ cm, maintains the stability of Si n+p shallow junction diodes with a 400 nm Cu overlayer up to 850 °C for 30 min vacuum annealing. When it is used between Al and Si, the highest temperature of stability achievable with a 100-nm-thick film is 550 °C. A thermal treatment at 600 °C causes a severe intermixing of the layers. The microstructure, atomic density, and electrical resistivi...

Abstract: In this article, we propose an amorphouslike chemical vapor deposited tungsten (CVD-W) thin film as a diffusion barrier for copper metallization. Experimental results gave no evidence of interdiffusion and structural change for Cu/amorphouslike CVD-W/Si samples annealed up to 675 °C for 30 min in N2. At higher temperatures (700 °C), Cu penetration results in the formation of η′′-Cu3Si precipitates at the CVD-W/Si interface. This is due to the crystallization of the amorphouslike CVD-W film above 650 °C, rendering the grain-boundary structure and, hence, fast pathways for Cu diffusion. The Cu/amorphouslike CVD-W/p+n diodes, thus, sustain large increases in reverse leakage current. In addition, the effects of nitrogen addition by using an in situ nitridation on the amorphouslike CVD-W film are also discussed. The effectiveness of the nitrided barrier is attributed to the blocking of the grain boundaries in the tungsten film by nitrogen atoms. This slows down Cu diffusion significantly. Physical and chemical...

Abstract: There is provided a surface alloyed component which comprises a base alloy with a diffusion barrier layer enriched in silicon and chromium being provided adjacent thereto. An enrichment pool layer is created adjacent said diffusion barrier and contains silicon and chromium and optionally titanium or aluminum. A reactive gas treatment may be used to generate a replenishable protective scale on the outermost surface of said component.

Abstract: A method for making air-insulated planar metal interconnections having low interlevel capacitance with improved RC time delays for integrated circuits is achieved. The method involves using a multilayer of negative and positive photoresists in which open regions are developed in the negative photoresist for the metal interconnections, and open regions are developed in the positive photoresist for via holes. The open regions are then filled with a Ti/TiN diffusion barrier deposited at room temperature and an electroless plated copper, and polished back using a Dual Damazene to form the interconnecting metal level and the via hole stud. The method is repeated several times to form multilevel metal interconnections. The remaining photoresist is then totally removed by oxygen ashing to leave a free-standing multilevel metal interconnection structure that is conformally coated with a thin Al 2 O 3 passivation layer and having air insulation. This results in a much lower inter- and intralevel capacitance and improved circuit performance.

Abstract: In order to provide a thermally stable diffusion barrier for a contact, a layer of titanium is formed on the patterned substrate. A layer of tungsten nitride is formed on the titanium layer. After an annealing step, an interfacial layer and a layer of titanium nitride are formed between the substrate and a tungsten layer. These layers provide a diffusion barrier which is more thermally stable than a titanium nitride layer applied directly on the substrate and permits the formation of a contact structures that can withstand subsequent high temperature steps.

Abstract: Annealing in O2 at temperatures above 650° C is required for a thin ferroelectric capacitor. Reduction of the leakage current and an increase of capacitance can be attained in the charge storage capacitor through this annealing. A stacked structure capacitor cell must be practically employed in metal oxide semiconductor large scale integrated circuits (MOSLSI). In this capacitor cell with a conventional Pt/TiN/poly-Si lower electrode, however, O2 annealing can not be attained at high temperature because peeling of the TiN barrier layer and the formation of a thin oxide layer at the surface of poly-Si occur. An noncrystalline TaSiN layer has been studied with respect to the barrier effect for oxygen diffusion used in the barrier layer of the lower electrode. The penetration depth of oxygen diffusion decreases markedly with increasing Si composition in a TaSiN layer and reaches 20 nm deep in a Ta.22Si.35N.43 layer. However, the resistivity increases with this increase. A good diffusion barrier layer with low sheet resistance is attained in a Ta.50Si.16N.34 layer. Penetration depth below 40 nm is obtained in a slightly Si-rich Ta.36Si.27N.37 layer for O2 annealing at 850° C.

Abstract: Results are presented from a systematic study of the composition, texture, and electrical properties of titanium nitride (TiN) films and their performance as diffusion barrier in multilevel interconnect schemes of ultralarge scale integration (ULSI) computer chip device structures. The films were grown by low temperature (<450°C) inorganic chemical vapor deposition using titanium tetraiodide as source precursor and ammonia and hydrogen as co-reactants. The TiN films were nitrogen-rich., with iodine concentrations below 2 atom percent, displayed resistivities in the range 100 to 150 μΩ cm depending on thickness, and exhibited excellent step coverage with better than 90% conformality in both nominal 0.45 μm, 3:1 aspect ratio and 0.25 μm, 4:1 aspect ratio contact structures. A comparison of the properties of chemical vapor deposited (CVD) TiN with equivalent physical vapor deposited (PVD) TiN showed that reactivity with Al-0.5 a/o Cu alloys was equivalent in both cases. In particular, a 10% increase in the Al-Cu/TiN stack sheet resistance was observed for both types of TiN after a 450°C, 30 min sinter. Similarly, the characteristics of CVD tungsten and reflow plug fills were identical on both types of TiN films. However, barrier performance for CVD TiN in aluminum and tungsten plug technologies was superior to that of PVD TiN, as evidenced by lower contact diode leakage for CVD TiN in comparison with PVD TiN films of equal thickness. This improved barrier performance could be attributed to a combination of factors, which include the nitrogen-rich composition, higher density, and enhanced conformality of the CVD TiN phase in comparison with the PVD TiN. In view of the superior step coverage and diffusion barrier characteristics, the low temperature inorganic CVD route to TiN seems to provide an adequate replacement for conventional PVD TiN in emerging ULSI metallization interconnect schemes.

Abstract: Methods of forming integrated circuit capacitors include the steps of forming an electrically insulating layer having a contact hole therein, on a face of a semiconductor substrate and then forming a polysilicon contact plug in the contact hole. A first capacitor electrode is then formed in electrical contact with the polysilicon contact plug. The first capacitor electrode may be formed by etching a composite of a diffusion barrier metal layer containing a nitride material (or silicide material) and a first electrically conductive layer. Alternatively, the first capacitor electrode may be formed by etching the diffusion barrier metal layer without the first electrically conductive layer thereon. The diffusion barrier metal layer inhibits parasitic migration of silicon from the polysilicon plug to the first electrically conductive layer. A protective layer of a preferred material is then electroplated onto an upper surface and on sidewalls of the first capacitor electrode. The protective layer is designed to protect exposed sidewall portions of the barrier metal layer from being oxidized during subsequent process steps. Next, a capacitor dielectric layer is formed on the protective layer, opposite the upper surface of the first capacitor electrode. The capacitor dielectric layer is preferably formed of a high dielectric material such as a material selected from the group consisting of Ta 2 O 5 , SrTiO 3 , BaTiO 3 , SrTiO 3 , (Ba, Sr)TiO 3 , Pb(Zr, Ti)O 3 , SrBi 2 Ta 2 O 9 (SBT), (Pb,La)(Zr, Ti)O 3 and Bi 4 Ti 3 O 12 .

Abstract: Novel structures for capacitors which are capable of withstanding heat treatments to at least 400° C. while providing low defect densities and low electrical series resistance in its electrodes are disclosed. In one embodiment of the present invention, a capacitor structure includes a bottom capacitor electrode formed of a first sub-layer of aluminum, a second sub-layer of tantalum nitride, and a third sub-layer of tantalum. The capacitor structure further includes a sputtered dielectric layer of tantalum pentoxide over the tantalum sub-layer of the bottom electrode. The resulting structure is anodized such that the underlying tantalum layer is fully anodized, and preferably such that a portion of the tantalum nitride layer is converted to a tantalum oxy-nitride. The tantalum nitride layer was discovered by the inventors to act as a good high temperature diffusion barrier for the aluminum, preventing the aluminum from migrating into the anodized tantalum pentoxide layer under high temperature processing conditions, where it would chemically reduce the tantalum atoms in the tantalum pentoxide layer and introduce conductive paths of tantalum in the dielectric (tantalum pentoxide) layer. The aluminum layer provides good electrical conductivity for the bottom electrode, and is anodized to fill any pinhole defects in the layers formed above it, thereby increasing manufacturing yields.

Abstract: This has been accomplished in the past using four/five separate electrode- and diffusion-barrier layers. In this letter, we report a novel Pt–Rh–Ox/Pt–Rh/Pt–Rh–Ox electrode-barrier structure which acts as an electrode as well as a diffusion barrier for integration of the ferroelectric capacitors directly onto silicon deposited using an in situ reactive rf sputtering process. The electrodes have a smooth and fine grained microstructure and are excellent diffusion barriers between the PbZr0.53Ti0.47O3 (PZT) and Si substrate and exhibit good thermal stability up to very high processing temperatures of 700 °C. The ferroelectric (PZT) test capacitors using these electrode barriers grown directly on Si, show well saturated hysteresis loops with Pr and Ec of 16 μC/cm2 and 30–40 kV/cm, respectively. The capacitors exhibit no significant fatigue loss (<5%) up to 1011 cycles and have low leakage currents (2×10−8 A/cm2 at 100 kV/cm). These electrode barriers can be used to directly integrate the thin film capacitors...

Abstract: In a semiconductor memory device, a tantalum silicon nitride film or hafnium silicon nitride film is provided, as a diffusion barrier layer, between a polysilicon plug which electrically connects a source/drain region to a lower platinum electrode of a capacitor, formed on a silicon substrate, and the lower platinum electrode. The tantalum silicon nitride film has a composition of TaX Si1-X NY wherein 0.75 ≦X≦0.95 and 1.0 ≦Y≦1.1. The hafnium silicon nitride film has a composition of HfX Si1-X NY wherein 0.2