TL;DR: A copper metallization structure and process for the formation of electrical interconnections fabricated with pure copper metal is provided in this article, which includes an interface layer (22) intermediate to a dielectric layer (12), and a copper interconnect (30).
Abstract: A copper metallization structure and process for the formation of electrical interconnections fabricated with pure copper metal is provided. The metallization structure includes an interface layer (22) intermediate to a dielectric layer (12), and a copper interconnect (30). The interface layer (22) functions to adhere the copper interconnect (30) to a device substrate (10) and to prevent the diffusion of copper into underlying dielectric layers. The interconnect layer (22) is fabricated by depositing a first titanium layer (16) followed by the sequential deposition of a titanium nitride layer (18), and a second titanium layer (20). A copper layer (24) is deposited to overlie the second titanium layer (20) and an annealing step is carried out to form a copper-titanium intermetallic layer (26). The titanium nitride layer (18) functions as a diffusion barrier preventing the diffusion of copper into the underlying dielectric layer (12), and the copper titanium intermetallic layer (26) provides an adhesive material, which adheres the copper layer (24) to the device substrate ( 10). Following the formation of the intermetallic layer (26), the device surface is planarized to form a planar surface (28), and to form an inlaid copper interconnect (30).
TL;DR: In this paper, the diffusion constants of oxygen in each of the three layers were derived based on X-ray microanalysis, Xray diffraction, and resistance measurements, and the results indicated that the oxide interlayer is a better diffusion barrier for oxygen than either of the other layers.
Abstract: After hafnium carbide has been oxidized at temperatures in the range of 1400° to 2060°C, three distinct layers are present in the film cross section: (a) a residual carbide layer with dissolved oxygen in the lattice, (b) a dense-appearing oxide interlayer containing carbon, and (c) a porous outer layer of hafnium oxide. Experimental measurements of layer thicknesses and oxygen concentrations are combined with an extended formulation of moving-boundary diffusion theory to obtain the diffusion constants of oxygen in each of the three layers. The results indicate that the oxide interlayer is a better diffusion barrier for oxygen than either of the other layers. Based on X-ray microanalysis, X-ray diffraction, and resistance measurements, the interlayer is an oxygen-deficient oxide of hafnium with a carbon impurity. The interlayer hardness equals that of the residual carbide layer.
TL;DR: In this article, the effects of deposition pressure, in situ oxygen dosing at interfaces, hydrogen and oxygen contamination, and microstructure on diffusion barrier performance to Cu diffusion for electron-beam deposited Ta are presented.
Abstract: We demonstrate that depositing Ta diffusion barriers under ultra‐high vacuum conditions without in situ oxygen dosing allows for variations both in microstructure and in the concentration of chemical impurities that severely degrade barrier performance. The effects of deposition pressure, in situ oxygen dosing at interfaces, hydrogen and oxygen contamination, and microstructure on diffusion barrier performance to Cu diffusion for electron‐beam deposited Ta are presented. 20 nm of Ta diffusion barrier followed by a 150 nm Cu conductor were deposited under ultra‐high vacuum (UHV, deposition pressure of 1×10−9 to 5 ×10−8 Torr) and high vacuum (HV, deposition pressure of 1×10−7 to 5×10−6 Torr) conditions onto 〈100〉 Si. In situ resistance furnace measurements, Auger compositional depth profiling, secondary ion mass spectrometry, and forward recoil detection along with scanning and transmission electron microscopy were used to determine the electrical, chemical, and structural changes that occurred in thin‐film Ta diffusion barriers upon annealing. Undosed HV deposited Ta barriers failed from 560 to 630 °C, while undosed UHV barriers failed from 310 to 630 °C. For UHV Ta barriers, in situ oxygen dosing during deposition at the Cu/Ta interface increased the failure temperatures by 30–250 °C and decreased the range of failure temperatures to 570–630 °C. Undosed UHV Ta barriers have no systematic relationship between failure temperature and deposition pressure, although correlations between breakdown temperature, oxygen and hydrogen concentrations, and microstructural variations were measured.
TL;DR: In this article, the nucleation mechanisms of Cu film growth on TiN during MOCVD were investigated using x-ray photoelectron spectroscopy and temperature programmed desorption mass spectrometry in an ultrahigh vacuum (UHV) system.
Abstract: Cu is receiving increasing attention as a replacement for Al in future Si ultra‐large‐scale integrated circuits due to its lower resistivity and potentially better reliability in terms of electromigration resistance and stress‐induced voiding. Metalorganic chemical vapor deposition (MOCVD) of Cu offers the advantages of conformal coverage and selective growth. Whatever the means of deposition, a diffusion barrier and adhesion layer such as TiN is required. To understand the nucleation mechanisms of Cu film growth on TiN during MOCVD, we have studied the thermal decomposition of two metalorganic precursors, hexafluoroacetylacetonate Cu(I) vinyltrimethylsilane [CuI(hfac)(vtms)], and bis (hexafluoroacetylacetonate) Cu(II) [CuII(hfac)2] by x‐ray photoelectron spectroscopy and temperature programmed desorption mass spectrometry in an ultrahigh vacuum (UHV) system.Experiments were carried out on polycrystalline air‐exposed (i.e., oxidized) TiN and N2 ion beam sputter‐cleaned TiN. These surfaces are representati...
TL;DR: In this paper, the authors proposed a method for capping a low resistivity metal conductor line or via with a refractory metal using chemical-mechanical polishing techniques.
Abstract: Capping a low resistivity metal conductor line or via with a refractory metal allows for effectively using chemical-mechanical polishing techniques because the hard, reduced wear, properties of the refractory metal do not scratch, corrode, or smear during chemical-mechanical polishing. Superior conductive lines and vias are created using a combination of both physical vapor deposition (e.g., evaporation or collimated sputtering) of a low resistivity metal or alloy followed by chemical vapor deposition (CVD) of a refractory metal and subsequent planarization. Altering a ratio of SiH₄ to WF₆ during application of the refractory metal cap by CVD allows for controlled incorporation of silicon into the tungsten capping layer. Collimated sputtering allows for creating a refractory metal liner (15) in an opening (14) in a dielectric (11-13) which is suitable as a diffusion barrier to copper based metallizations (16) as well as CVD tungsten. Ideally, for faster diffusing metals like copper, liners are created by a two step collimated sputtering process wherein a first layer is deposited under relatively low vacuum pressure where directional deposition dominates (e.g., below 1mTorr) and a second layer is deposited under relatively high vacuum pressure where scattering deposition dominates (e.g., above 1mTorr). For refractory metals like CVD tungsten, the liner can be created in one step using collimated sputtering at higher vacuum pressures.
TL;DR: In this paper, the diffusion of boron in N2 ambient is studied by using p+ polysilicon metaloxide-silicon structures annealed during times long enough to allow bors diffusion through the gate oxide, up to the underlying substrate.
Abstract: The diffusion of boron in N2 ambient is studied by using p+ polysilicon metal‐oxide‐silicon structures annealed during times long enough to allow boron diffusion through the gate oxide, up to the underlying substrate. Assuming equilibrium segregation at the interfaces, the boron diffusivity in the oxide is calculated by numerically fitting the resulting profile in the substrate. It is found that B diffuses in SiO2 with an activation energy of about 3 eV. We also quantify the influence of the nitridation of the oxide, and confirm its efficiency as a diffusion barrier. However, this study reveals a strong inconsistency between the extracted diffusivity values of B in SiO2 and the amount of B atoms being able to reach the Si/SiO2 interface to account for the observed interface state density.
TL;DR: In this article, a physical vapour deposition, diffusion barrier coating in the system A1-O-N offers the possibility to reduce the interdiffusion between the layers of MCrA1Y and the Ni-base material, and was tested up to 400 h at 1100°C in annealing tests and up to 2500 cycles in a thermal fatigue test rig with 1115°C and 200°C as the high and low peak temperatures.
Abstract: A physical vapour deposition, diffusion barrier coating in the system A1-O-N offers the possibility to reduce the interdiffusion between the layers of MCrA1Y and the Ni-base material. The barrier function depends on the high temperature stabilization of the amorphous structure. While amorphous A1-O undergoes modification at 1100°C from several crystalline substructures up to the ϵ phase, A1-O-N remains in the amorphous structure at 1100°C. This coating acts successfully as a passive diffusion barrier, and was tested up to 400 h at 1100°C in annealing tests and up to 2500 cycles in a thermal fatigue test rig with 1115°C and 200°C as the high and low peak temperatures. The gradient-free transition step achieved in the element analysis of the depth profiles, together with the inspection of the cross-sections, confirm the excellent barrier performance.
TL;DR: In this article, the authors showed that the native oxide layer works like a diffusion barrier, and the effect of an interposed TiNx layer on the diffusion behavior has also been investigated.
Abstract: Cu thin films have been deposited on Si(111) substrates with two different initial conditions. In one, the substrates had a top native oxide layer, and in the other the native oxide layer was etched in hydrofluoric acid and the etched surface was treated with a bromine-methanol solution prior to the surface being exposed to atmosphere. This Br-treatment is known to saturate surface dangling bonds on an Si(111) surface. Vacuum annealing of the Cu/Si samples, followed by Rutherford backscattering spectrometry (RBS) measurements showed the onset temperature of interdiffusion to be ∼ 220°C for the Si(111) substrate treated with bromine-methanol solution whereas the onset temperature of interdiffusion was found to be between 600°C and 700°C for Si(111) surfaces with native oxide on top. This shows that the native oxide layer works like a diffusion barrier. The effect of an interposed TiNx layer on the diffusion behaviour has also been investigated. A thin layer ( 600°C) for the Cu/SiO2/Si(111) suggests that SiO2 introduces the highest barrier for Cu-Si interdiffusion among all the barrier combinations studied here. At annealing temperatures above the onset temperature of interdiffusion copper silicides are formed. RBS simulations have been used to study the compositions of the reacted films.
TL;DR: In this paper, a resistivity of 63.5 μ Ω−cm was obtained at 900°C for a (101) grain rather than a preferential (110) grain for diffusion barrier layers.
Abstract: Ruthenium dioxide films for diffusion barrier layers are deposited by reactive sputtering in oxygen atmospheres at different conditions. Stoichiometric films are deposited at oxygen partial pressures above 4.8 mTorr. When annealing is done for this film, a (101) grain rather than a preferential (110) is grown. Stoichiometric films can be deposited at lower oxygen partial pressures when the deposition is performed at lower power. For this film at lower power, however, (101) grain is preferentially grown with this annealing. A resistivity of 63.5 μ Ω‐cm is obtained at 900°C.
TL;DR: In this paper, a new method of fabricating a polycide gate structure is described, where a gate polysilicon layer is provided overlying a gate oxide layer on the surface of a semiconductor substrate.
Abstract: A new method of fabricating a polycide gate structure is described A gate polysilicon layer is provided overlying a gate oxide layer on the surface of a semiconductor substrate A thin conducting diffusion barrier layer is deposited overlying the gate polysilicon layer A layer of tungsten silicide is deposited overlying the thin conducting diffusion barrier layer wherein a reaction gas used in the deposition contains fluorine atoms and wherein the fluorine atoms are incorporated into the tungsten silicide layer The gate polysilicon, thin conducting diffusion barrier, and tungsten silicide layers are patterned to form the polycide gate structures The wafer is annealed to complete formation of the polycide gate structures wherein the number of fluorine atoms from the tungsten silicide layer diffusing into the gate polysilicon layer are minimized by the presence of the thin conducting diffusion barrier layer and wherein because the diffusion of the fluorine atoms is minimized, the thickness of the gate oxide layer does not increase This prevents the device from degradation such as threshold voltage shift and saturation current decrease
TL;DR: In this paper, a diffusion barrier is placed within a polysilicon gate material to prevent the impurity from diffusing to underlying silicon-oxide bonds residing within the oxide bulk, and the barrier comprises Ar atoms placed in fairly close proximity to one another within the gate conductor.
Abstract: A PMOS device is provided having a diffusion barrier placed within a polysilicon gate material. The diffusion barrier is purposefully implanted to a deeper depth within the gate material than subsequently placed impurity dopants. The barrier comprises Ar atoms placed in fairly close proximity to one another within the gate conductor, and the impurity dopant comprises ions of BF2. F from the impurity dopant of BF2 is prevented from diffusing to underlying silicon-oxide bonds residing within the oxide bulk. By minimizing F migration to the bond sites, the present polysilicon barrier and method of manufacture can minimize oxygen dislodgment and recombination at the interface regions between the polysilicon and the gate oxide as well as between the gate oxide and silicon substrate.
TL;DR: A planar polarographic sensor for determining the lambda value of gas mixtures, for use with exhaust gases in internal combustion engines, includes a planar ceramic carrier sheet having an outer and inner pumping electrode respectively arranged on opposite planar sides thereof, and a diffusion barrier as discussed by the authors.
Abstract: A planar polarographic sensor for determining the lambda value of gas mixtures, for use with exhaust gases in internal combustion engines, includes a planar ceramic carrier sheet having an outer pumping electrode and an inner pumping electrode respectively arranged on opposite planar sides thereof, and a diffusion barrier. The outer and inner pumping electrodes, and the diffusion barrier are arranged on the planar ceramic carrier sheet so that the measuring gas is fed via the diffusion barrier to the inner pumping electrode. The sensor has front and side edge faces. The diffusion barrier is configured as a diffusion layer at least partially covering the inner pumping electrode and exposed at least at one edge face of the sensor to the measuring gas. A diffusion-free planar region of the sensor is provided with an equalizing layer having the same thickness as the diffusion layer, and the equalizing layer is disposed in the same plane with and adjacent to the diffusion layer.
TL;DR: In this article, a contact diffusion barrier is formed by implanting a second material into a low resistivity material that overlies the semiconductor to which contact is desired, and the resulting barrier is self-aligned with the contact opening, and is established only in the immediate vicinity of the opening.
Abstract: A method of forming a contact diffusion barrier in a thin geometry integrated circuit device involves implanting a second material into a low resistivity material that overlies the semiconductor to which contact is desired. The low resistivity and implanted materials are selected to intereact with each other and form a contact diffusion barrier. Both materials may include transition metals, in which case the diffusion barrier is a composite transition metal. Alternately, the low resistivity material may include a transition metal, while implantation is performed with nitrogen. The implantation is performed by plasma etching, preferably with active cooling, which can be combined in a continuous step with the etching of the contact opening. The resulting contact diffusion barrier is self-aligned with the contact opening, and is established only in the immediate vicinity of the opening.
TL;DR: In this paper, the authors investigated the nature of rate-controlling interfacial reactions in epitaxial Al/Ti1−xAlxN thin-film couples using annealing at Ta=600°C for up to 150 min.
Abstract: Transmission electron microscopy (TEM), cross‐sectional TEM, scanning TEM with energy dispersive x‐ray analysis, and Auger electron spectroscopy were used to investigate the nature of rate‐controlling interfacial reactions in epitaxial Al/Ti1−xAlxN thin‐film couples. TiN and NaCl‐structure Ti1−xAlxN layers, 120 nm thick, with compositions x=0.1 and 0.2 were grown on MgO(001) substrates by ultrahigh vacuum reactive magnetron cosputter deposition in N2 discharges. Epitaxial Al films, 200‐nm‐thick, were then grown in Ar on top of the nitride layers during the same vacuum cycle. The reaction paths for Al/TiN and Al/(Ti,Al)N interactions during anneals at Ta=600 °C for ta up to 150 min was similar, but the extent of reaction was dramatically decreased by the substitution of (Ti,Al)N barrier layers for TiN. The primary mobile species during annealing was Ti which penetrated into the Al layers and reacted to form the ordered tetragonal intermetallic phase Al3Ti while Al segregation resulted in the formation of a...
TL;DR: In this article, a diffusion barrier is placed within the polysilicon gate to prevent penetration of boron atoms through the gate oxide and into the channel region, which helps prevent change in channel concentration.
Abstract: A PMOS device is provided having a diffusion barrier placed within the polysilicon gate. The diffusion barrier is purposefully deposited to a concentration peak density within the gate which is deeper than subsequently placed impurity dopant. The barrier comprises germanium atoms placed in fairly close proximity to one another within the gate conductor, and the impurity dopant comprises an ionized compound of BF2 subsequently placed as boron within the gate and source/drain region, at least a majority and preferably greater than eighty percent of which are placed shallower within the gate than the germanium atoms. The barrier region substantially prevents or retards penetration of boron atoms through the gate oxide and into the channel region. Thus, the barrier helps prevent change in channel concentration and problems associated with boron penetration such as flatband voltage (Vfb) and threshold voltage (Vth) shift.
TL;DR: In this article, the feasibility of electroless deposits as a diffusion barrier between solder and aluminum pad was investigated with the aid of scanning Auger microscopy and X-ray diffraction (XRD).
TL;DR: In this article, an improved method for depositing a thin copper aluminum alloy film on a patterned silicon substrate is described, where the base layer conforming to the existing pattern is initially formed on the surface of the substrate, followed by contact with vapors of an aminealane compound, which causes aluminum to be selectively deposited on the copper base layer portion.
Abstract: An improved method is provided for depositing a thin copper aluminum alloy film on a patterned silicon substrate A copper base layer conforming to the existing pattern is initially formed on the surface of the substrate, followed by contact with vapors of an aminealane compound, which causes aluminum to be selectively deposited on the copper base layer portion of the substrate Preferably, copper is applied to a diffusion barrier surface such as tungsten using chemical vapor deposition from a complex of copper (I) perfluoroalkyl-β-diketonate and an olefin or silylolefin The entire process of developing an alloy film can be carried out without exceeding 200°C
TL;DR: In this article, a method of electrically connecting a tape automated bonding lead (28) to an aluminum input/outpout pad (10) of an integrated circuit includes sequentially sputtering an adhesive layer (16), a diffusion barrier layer (18), and a gold layer (20) on the input/output pad.
Abstract: A method of electrically connecting a tape automated bonding lead (28) to an aluminum input/outpout pad (10) of an integrated circuit includes sequentially sputtering an adhesive layer (16), a diffusion barrier layer (18) and a gold layer (20) on the input/output pad (10). The adhesive layer (16) is a metallic film having good step coverage and adhesive properties to contact the pad (10). The diffusion barrier layer (18) is formed atop the adhesive layer (16) and is sandwiched by the gold layer (20). The method employs 'bumpless' techniques and the bond lead (28) is connected to the gold layer (20) by applying a combination of pressure and vibrational energy.
TL;DR: In this article, a self-aligned diffusion barrier or seed layer is formed in an integrated circuit and a dielectric layer is then formed and the sacrificial material is subsequently removed to expose the underlying seed layer.
Abstract: Metallization having a self-aligned diffusion barrier or seed layer is formed in an integrated circuit. In one embodiment of the invention, a sacrificial material (20) is used to define a seed layer (24). A dielectric layer (26) is then formed and the sacrificial material (20) is subsequently removed to expose the underlying seed layer (24). A conductive layer of material (32), such as copper, is then selectively deposited onto the seed layer (24). Because the diffusion barrier or seed layer is self-aligned the metal to metal spacing in an integrated circuit may be reduced. Therefore, integrated circuits having high device packing densities can be fabricated.
TL;DR: In this article, the effects of a thin interfacial native oxide layer on the electronic properties and stability of a Au/(100) n−GaAs contact as a function of time were investigated.
Abstract: Ballistic electron emission microscopy (BEEM) has been used to investigate the effects of a thin interfacial native oxide layer on the electronic properties and stability of a Au/(100) n‐GaAs contact as a function of time. The oxide had no effect on the electronic band structure at the interface measured with BEEM, as compared to similar contacts without a diffusion barrier. In addition, the oxide greatly enhanced the electrical homogeneity of the interface and prolonged the ability of the diode to transmit ballistic electrons to more than 35 days.
TL;DR: In this article, an NFET is positioned between field oxide regions 12, 14 of a P-type S semiconductor-substrate 10, and a PFET 20 is placed between field polysilicon oxide regions 14, 16, and an oxide layer 50 is formed on a coating layer 48 containing a mixture of titanium oxide and tungsten oxide.
Abstract: PURPOSE: To manufacture a semiconductor device, which can improve barrier characteristics of a diffusion barrier material layer on a board readily, with good time efficiency by forming a thin oxide layer on a barrier metallic layer by oxidizing a barrier material layer by immersing a board in oxide solution CONSTITUTION: An NFET 18 is positioned between field oxide regions 12, 14 of a P-type S semiconductor-substrate 10, and a PFET 20 is positioned between field oxide regions 14, 16 Then, the board 10 is immersed in nitric acid at a room temperature, and an oxide layer 50 is formed on a coating layer 48 The oxide layer 50 contains a mixture of titanium oxide and tungsten oxide The oxide layer 50 formed in this way is 10 to 20Å thick with respect to immersion of 15 minutes, for example Barrier characteristics of a diffusion barrier material layer on the board 10 can be improved readily with good time efficiency, by forming a thin oxide film on a barrier metallic layer from oxidizing a barrier material layer in immersing the board 10 in an oxide solution this way
TL;DR: In this paper, the effectiveness of several coating systems which were used as a diffusion barrier for the SiC fiber-reinforced titanium aluminide composites was investigated, and the results show that none of the above coating systems can satisfy the requirements for a strong, tough, and damage-tolerant SiC-fiber reinforced titanium alumnide composite.
Abstract: The effectiveness of several coating systems which were used as a diffusion barrier for the SiC fiber-reinforced titanium aluminide composites was investigated. TaC, TiC, TiB2, B, C/graded TiB2, and Ag/Ta were applied to the SiC fiber via chemical vapor deposition and physical vapor deposition. The interfacial compatibility, interfacial stability, thermal residual stress, interfacial bond strength, and the transverse fracture behavior of the composites with coated fibers were characterized and determined. The results show that none of the above coating systems can satisfy the requirements for a strong, tough, and damage-tolerant SiC fiber-reinforced titanium aluminide composite. Several multilayer, multifunctional coating systems are proposed.
TL;DR: The use of consecutively sputtered Ti/Co layers for the silicidation of Si implanted with 2 × 1015 As or B/cm2 has been investigated in this paper, where it has been observed that the reaction is slowed down by the presence of the Ti layer, which acts as a diffusion barrier.
TL;DR: In this paper, the existence of a non-magnetic interfacial amorphous layer due to interdiffusion over very short distances during deposition of Ni-Ti multilayers was shown.
TL;DR: The value of the room temperature copper-gold interdiffusion coefficient derived by extrapolating from high-temperature measurements is an underestimate by several orders of magnitude as discussed by the authors, due to the electrical resistivity of an alloy being much higher than that of either component.
Abstract: The value of the room-temperature copper-gold interdiffusion coefficient derived by extrapolating from high-temperature measurements is an underestimate by several orders of magnitude. Plating copper with a gold film has several disadvantages. Two specimens were analyzed by using Auger electron spectroscopy. Once the full thickness of the gold film is penetrated, copper accumulates on the surface, and a layer of high concentration of copper exists immediately below the gold-air interface. Electrical resistivity of an alloy is much higher than the resistivity of either component. This high-resistivity layer may be localized within the skin depth of propagating electromagnetic waves; in cases where copper has reached the surface, it is permanently within the skin depth at any frequency. A nickel diffusion barrier, commonly applied between copper and gold, is unsuitable in many microwave and millimeter-wave applications because of ferromagnetism of nickel at room temperature. The compound that forms on the surface of untreated copper at room temperature in a reasonably clean atmosphere is cuprous oxide. Its properties make it a better alternative to gold in microwave and millimeter-wave engineering. >
TL;DR: In this paper, the microstructure of thin films is characterized from both macro and micro points of view with the use of Auger electron spectroscopy, X-ray diffraction, electron probe microanalysis and high resolution field emission scanning electron microscopy.
TL;DR: In this paper, the thermal stability of PECVD-W-N thin film was investigated as a diffusion barrier between Al or Au and Si during subsequent annealing at 550-850°C.
Abstract: The thermal stability of plasma-enhanced chemical-vapor-deposited tungsten nitride (PECVD-W-N) thin film has been investigated as a diffusion barrier between Al or Au and Si during subsequent annealing at 550-850°C. The atomic concentrations of N in as-deposited W100-xNx films are varied from 0 to 75 at.% corresponding to NH3/WF6 ratio, and their resistivities are varied from 10-460 µΩcm. Rutherford backscattering spectrometry, Auger electron depth profiles, X-ray diffraction and transmission electron microscopy show that 900 A PECVD-W67N33 film interposed between Al or Au and Si is less permeable than sputtered TiN and PECVD-W film due to interstitial N atoms and Si/W67N33/Au maintaining the integrity of interface while the furnace post annealing is carried out at 850°C for 30 min.
TL;DR: In this paper, the diffusion barrier properties of Ta, Ta-N and TaN films to Si and the Cu9Al4 compound have been studied by examining depth profiles obtained from Auger electron spectroscopy.
Abstract: The diffusion barrier properties of Ta, Ta-N and TaN films to Si and the Cu9Al4 compound have been studied by examining depth profiles obtained from Auger electron spectroscopy. The contact system degrades with the silicide formation at the interface between the barrier and the Si substrate. The silicide formation temperature of these films was 650°C for the Ta barrier and 700°C for the Ta-N one. The contact system using the TaN compound barrier tolerates a temperature of 750°C. Ta atoms are the diffusing species for silicide formation in the present study, which protects the contact system from catastrophic failure due to the intermixing of all elements at higher temperatures.
TL;DR: In this article, the concept of the buffer layer has been utilized and good quality Y1Ba2Cu3O7- delta (YBCO) thin films have been fabricated on Hastelloy (C), Inconel (600) and stainless steel (304) with titanium nitride (TiN) buffer layers.
Abstract: Deposition of high-quality Y1Ba2Cu3O7- delta (YBCO) thin films on technologically important substrates such as stainless steel or high-temperature structural Ni-based superalloys is a difficult problem due to inherent interdiffusion problems between substrates and superconducting overlayers. To overcome this difficulty the concept of the buffer layer has been utilized and good quality YBCO thin films have been fabricated on Hastelloy (C), Inconel (600) and stainless steel (304) with titanium nitride (TiN) buffer layers. TiN is an excellent choice as a barrier layer on these metallic substrates due to low diffusivity, high thermal stability and thermal coefficient of expansion matching with the substrates. Because of the matching of the thermal expansion coefficient of TiN ( approximately (8.0-9.0)*10-6 K-1) with substrates ( approximately (9-10)*10-6 K-1) and YBCO ( approximately (12-13)*10-6 K-1) and its diffusion barrier characteristics, good quality high-Tc films have been grown on all substrates by single-chamber in situ laser processing at 600 degrees C. The films were characterized by X-ray diffraction, four-point AC electrical resistivity, scanning electron microscopy and Auger electron spectroscopy (AES) techniques. AES depth profiling indicated no interdiffusion of Fe across the interface of TiN and substrates. c-axis-oriented good quality thin films (zero resistance above liquid nitrogen temperature and Jc approximately 104-105 A cm-2 at 77 K) were obtained on these substrates. Optimization of laser deposition parameters to obtain superconducting thin films on metallic substrates for practical applications will be discussed in this paper.
TL;DR: In this paper, a polysilicon layer is provided with a p-type impurity, and masked with an oxide mask to define a p type region of the poly silicon layer, which is then anisotropic etched to form spacers adjacent to the first oxide mask.
Abstract: A polysilicon layer is provided with a p-type impurity, and masked with an oxide mask to define a p-type region of the polysilicon layer. A second impurity is then provided into first unmasked regions of the polysilicon layer. A second oxide mask is deposited and anisotropically etched to form spacers adjacent to the first oxide mask. The spacers define two diffusion barrier regions of the polysilicon layer adjacent to the p-type region. An n-type impurity is then provided into second unmasked regions of the polysilicon layer to form two n-type regions adjacent the diffusion barrier regions. The diffusion barrier regions prevent cross diffusion of the p-type and the n-type impurities within the polysilicon layer, while also being of sufficient dimensions to permit normal p/n operations.