Die shrink

Abstract: Disclosed is a system, method, and computer-readable medium for designing a circuit and/or IC chip to be provided using an optical shrink technology node. Initial design data may be provided in a first technology node and through the use of embedding scaling factors in one or more EDA tools of the design flow, a design (e.g., mask data) can be generated for the circuit in an optical shrink technology node. Examples of EDA tools in which embedded scaling factors may be provided are simulation models and extraction tools including LPE decks and RC extraction technology files.

Abstract: Optical shrink for process migration, manufacturing process variation, temperature and voltage changes lead to clock skew as well as path delay variations in a manufactured chip. Such variations end up degrading the performance of manufactured chips. Since, such variations are hard to predict in pre-silicon phase, tunable clock buffers have been used in several designs. These buffers are tuned to improve maximum operating clock frequency of a design. Previously, we have presented an algorithmic approach that uses delay measurements on a few selected patterns to determine which buffers should be targeted for tuning. In this paper, a study on impact of tunable buffer placement on performance is reported. Greatest benefit from tunable buffer placement is observed, when the clock tree is designed by the proposed tuning system assuming random delay perturbations during design. Accordingly, we present a clock tree synthesis procedure which offer very good protection against process variation as borne out by the results.

Abstract: A probing system or process for electrical testing of a device fabricated on a wafer also conditions terminals such as solder balls on the device to improve uniformity of the heights of the terminals and improve the reliability of connections to an interconnect substrate in a flip-chip package or to a printed circuit board in a chip-on-board application. The system can employ a probe card that is a printed circuit board and/or is substantially identical to interconnect substrates used in flip-chip packaging. The probe card can be replaceable on a test head to allow for quick changes the reduce ATE downtime and to accommodate device changes such as a die shrink. Probe tips on the probe card can be the contact pads or bumps that are the normal electrical contact structures of the interconnect substrates.

Abstract: A probing system or process for electrical testing of a device also conditions terminals such as solder balls on the device to improve uniformity of the heights of the terminals and improve the reliability of connections to an interconnect substrate in a flip-chip package or to a printed circuit board in a chip-on-board application. The system can employ a probe card that is a printed circuit board, an interconnect substrate substantially such as used in flip-chip packaging of the device, or a semiconductor die similar to the device. The probe card can be replaceable on a test head to allow for quick changes that reduce ATE downtime and accommodate device changes such as a die shrink. Probe tips on the probe card can be the contact pads or bumps that are the normal electrical contact structures of the interconnect substrates or semiconductor dies.