Design layout record

Abstract: A silicon compilation system for CMOS operational amplifiers (OPASYN) is discussed. The synthesis system takes as inputs system-level specifications, fabrication-dependent technology parameters, and geometric layout rules. It produces a design-rule-correct compact layout of an optimized operational amplifier. The synthesis proceeds in three stages: (1) heuristic selection of a suitable circuit topology; (2) parametric circuit optimization based on analytic models; and (3) mask geometry construction using a macro cell layout style. The synthesis process is fast enough for the program to be used interactively at the system design level by system designers who are inexperienced in operational amplifier design. >

Abstract: A design system has been developed which is able to design transconductance amplifiers, operational amplifiers, low-noise BIMOS amplifiers, voltage and current references, quartz oscillators, comparators, and oversampled A/D converters including their digital decimation filter starting from building-block and technology specifications. This design system, called Interactive Design for Analog Circuits (IDAC), is able to size a library of analog schematics (actually more than 40) as a function of technology (p-well and n-well CMOS) and desired building-block specifications. IDAC also generates a complete data sheet, an input file for SPICE2, and an input file for the analog layout program ILAC.

Abstract: This preview guide presents the first 10 chapters of the our new title by Richard Jaeger: Microelectronic Circuit Design. This cutting edge new text develops a comprehensive understanding of the basic techniques of modern electronic circuit design, analog and digital, discrete and integrated. Digital electronics has evolved to be an extremely important area of circuit design, but it is included almost as an after-thought in the majority of introductory electronics texts. This book presents a much more balanced coverage of analog and digital circuits. The writing integrates the author's extensive industrial backround in precision analog and digital design with his many years of experience in the classroom.

Abstract: A method and system for performing layout verification on an integrated circuit (IC) design using reusable subdesigns. Many custom designed integrated circuits are designed and fabricated using a number of computer implemented automatic design processes. Within these processes, a high level design language (e.g., HDL or VHDL) description of the integrated circuit can be translated by a computer system into a netlist of technology specific gates and interconnections there between. The cells of the netlist are then placed spatially in an integrated circuit layout and the connections between the cells are routed using computerized place and route processes. Circuit designers next run layout verification tests on the layout to verify that the geometry and connectivity data of the design meets specific design rules and matches logically with the schematic representation. The present invention provides a method of layout verification where unchanged subdesigns of a hierarchical IC design can be reused upon subsequent verification processes of the same IC design. They are reused for both design rule checking (DRC) and layout versus schematic (LVS) comparison. By reusing some of the subcell designs, subsequent verification processes of the present invention can be performed very efficiently. To account for faults attributed to subcell interfaces, the present invention advantageously determines subcell overlap areas within the layout and selectively flattens and verifies these areas in addition to any subcell designs that were not previously validated. Further, the invention determines updated connectivity information for new subcell designs.