About: Dependent source is a research topic. Over the lifetime, 1618 publications have been published within this topic receiving 16930 citations. The topic is also known as: Editing Dependent source.
TL;DR: An accurate method is presented for simulating the power dissipation with use of a dependent current source and a parallel RC circuit for CMOS circuits.
Abstract: It becomes increasingly more important to reduce the power dissipation as the number of devices in VLSI increases. Accurate simulation of power dissipation is desirable while circuits are analyzed with circuit simulators such as SPICE. An accurate method is presented for simulating the power dissipation with use of a dependent current source and a parallel RC circuit. The steady-state voltage across the capacitor reads the average power drawn from the supply voltage source. Simulation results are shown for CMOS circuits.
TL;DR: This paper proposes to use the multivariate Gaussian source prior to achieve JBSS of sources that are linearly dependent across datasets, and introduces both Newton and quasi-Newton optimization algorithms for the general IVA framework.
Abstract: In this paper, we consider the joint blind source separation (JBSS) problem and introduce a number of algorithms to solve the JBSS problem using the independent vector analysis (IVA) framework. Source separation of multiple datasets simultaneously is possible when the sources within each and every dataset are independent of one another and each source is dependent on at most one source within each of the other datasets. In addition to source separation, the IVA framework solves an essential problem of JBSS, namely the identification of the dependent sources across the datasets. We propose to use the multivariate Gaussian source prior to achieve JBSS of sources that are linearly dependent across datasets. Analysis within the paper yields the local stability conditions, nonidentifiability conditions, and induced Cramer-Rao lower bound on the achievable interference to source ratio for IVA with multivariate Gaussian source priors. Additionally, by exploiting a novel nonorthogonal decoupling of the IVA cost function we introduce both Newton and quasi-Newton optimization algorithms for the general IVA framework.
TL;DR: In this paper, a flash EEPROM cell array is erased by applying a zero reference voltage to the bulk substrate of the cell, a relatively high negative voltage at the control gate of a cell and a relatively low positive voltage at or near the source region.
Abstract: A flash EEPROM cell array is erased by applying a zero reference voltage to the bulk substrate of the cell, a relatively high negative voltage to the control gate of the cell and a relatively low positive voltage to the source region of the cell. Because of a relatively low reverse voltage developed between the source region of the cell and the bulk substrate, the generation of hot holes is inhibited and improved performance may be obtained. The source region is preferably single diffused rather than double-diffused so that the cell can occupy a minimum area for a given design rule. The low positive voltage applied to the source is preferably less than or equal to the voltage, V CC presented at a +5V chip power supply pin. This makes it possible for the +5V pin to directly supply source current during erasure.
TL;DR: In this paper, a flash EEPROM cell array is erased by applying a relatively high positive voltage to the source region and a ground potential to the control gate of the cell while allowing the voltage of the drain region and the substrate region to float.
Abstract: A flash EEPROM cell array is erased by applying a relatively high positive voltage to the source region of the cell and a ground potential to the control gate of the cell while allowing the voltage of the drain region and the substrate region of the cell to float. By floating the substrate, the source current during erase is greatly reduced since the only DC current path is between the control gate and the source region. Since the source current is small, a double-diffused junction is not required so that the cell can occupy a minimum area for a given design rule and the cell fabrication process is simplified. In addition, the generation of high energy holes is suppressed and improved performance may be obtained. Because the source current is small during the erase operation, the high positive voltage at the source region can be generated by an on chip charge pump from a supply voltage as low as +3 V. This simplifies the design of memory boards on which many flash EEPROM chips are to be placed. Moreover, the after erase Vt distribution of the memory cell is tightened since a relatively high positive voltage is applied to the source region during erasure. Finally, there is no issue of yield sensitivity to defects in the channel, since during the erasure operation, electrons trapped in the floating gate pass through the overlap region between the source region and the control gate, instead of through the channel.
TL;DR: In this article, the performance of battery energy storage systems (BESS) models with different depths of detail is investigated and compared in a benchmark test microgrid, where an average model represented by voltage sources, an ideal dc source behind a voltage source converter, a back-to-back buck/boost and bidirectional three-phase converter are compared.
Abstract: With the increasing importance of battery energy storage systems (BESS) in microgrids, accurate modeling plays a key role in understanding their behavior. This paper investigates and compares the performance of BESS models with different depths of detail. Specifically, several models are examined: an average model represented by voltage sources; an ideal dc source behind a voltage source converter; a back-to-back buck/boost and bidirectional three-phase converter, with all models sharing the same control system and parameters; and two additional proposed models where the switches are replaced by dependent sources to help analyze the differences observed in the performance of the models. All these models are developed in PSCAD and their performances are simulated and compared considering various issues such as voltage and frequency stability and total harmonic distortion in a benchmark test microgrid. It is shown through simulation results and eigenvalue studies that the proposed models can exhibit a different performance, especially when the system is heavily loaded, highlighting the need for more accurate modeling under certain microgrid conditions.