Topic
Delay-locked loop
About: Delay-locked loop is a research topic. Over the lifetime, 5434 publications have been published within this topic receiving 66245 citations. The topic is also known as: DLL.
Papers published on a yearly basis
1 / 2
Papers
1 Nov 1996
TL;DR: In this article, a delay-locked loop (DLL) and phase-locked loops (PLL) designs based upon self-biased techniques are presented, which achieve process technology independence, fixed damping factor, fixed bandwidth to operating frequency ratio, broad frequency range, input phase offset cancellation, and low input tracking jitter.
Abstract: Delay-locked loop (DLL) and phase-locked loop (PLL) designs based upon self-biased techniques are presented. The DLL and PLL designs achieve process technology independence, fixed damping factor, fixed bandwidth to operating frequency ratio, broad frequency range, input phase offset cancellation, and, most importantly, low input tracking jitter. Both the damping factor and the bandwidth to operating frequency ratio are determined completely by a ratio of capacitances. Self-biasing avoids the necessity for external biasing, which can require special bandgap bias circuits, by generating all of the internal bias voltages and currents from each other so that the bias levels are completely determined by the operating conditions. Fabricated in a 0.5-/spl mu/m N-well CMOS gate array process, the PLL achieves an operating frequency range of 0.0025 MHz to 550 MHz and input tracking jitter of 384 ps at 250 MHz with 500 mV of low frequency square wave supply noise.
1,050 citations
TL;DR: A system to convert ambient mechanical vibration into electrical energy for use in powering autonomous low power electronic systems and an ultra low-power delay locked loop (DLL)-based system capable of autonomously achieving a steady-state lock to the vibration frequency is described.
Abstract: A system is proposed to convert ambient mechanical vibration into electrical energy for use in powering autonomous low power electronic systems. The energy is transduced through the use of a variable capacitor. Using microelectromechanical systems (MEMS) technology, such a device has been designed for the system. A low-power controller IC has been fabricated in a 0.6-/spl mu/m CMOS process and has been tested and measured for losses. Based on the tests, the system is expected to produce 8 /spl mu/W of usable power. In addition to the fabricated programmable controller, an ultra low-power delay locked loop (DLL)-based system capable of autonomously achieving a steady-state lock to the vibration frequency is described.
926 citations
TL;DR: This paper presents the derivation of these narrow correlator spacing improvements, verified by simulated and tested performance.
Abstract: Historically, conventional GPS receivers have used 1.0 chip early-late correlator spacing in the implementation of delay lock loop s (DLLs), However, there are distinct advantages to narrowing this spacing, especially in C/A-code tracking applications. These advantages are the reduction of tracking errors in the presence of both noise and multipath. The primary disadvantage i s that a wider precorrelation bandwidth is required, coupled with higher sample rates and higher digital signal processing rates. However, with current CMOS technology, this is easily achievable and well worth the price. Noise reduction is achieved with narrower spacing because the noise components of the early and late signals are correlated and ten d to cancel, provided that early and late processing are simultaneous (not dithered). Multipath effects are reduced because the DLL discriminator is less distorted by the delayed multipath signal. This paper presents the derivation of these narrow correlator spacing improvements, verified by simulated and tested performance.
842 citations
Book•
1 Jan 1996
TL;DR: In this article, a collection of 65 of the most important papers on phase-locked loops and clock recovery circuits is presented, with an extensive 40 page tutorial introduction and a comprehensive coverage of the field all in one self-contained volume.
Abstract: Featuring an extensive 40 page tutorial introduction, this carefully compiled anthology of 65 of the most important papers on phaselocked loops and clock recovery circuits brings you comprehensive coverage of the field-all in one self-contained volume. You'll gain an understanding of the analysis, design, simulation, and implementation of phase-locked loops and clock recovery circuits in CMOS and bipolar technologies along with valuable insights into the issues and trade-offs associated with phase locked systems for high speed, low power, and low noise.
527 citations
TL;DR: A dual delay-locked loop architecture which achieves low jitter, unlimited (modulo 2/spl pi/) phase shift, and large operating range, and the design of an experimental prototype in 0.8-/spl mu/m CMOS technology is described.
Abstract: This paper describes a dual delay-locked loop architecture which achieves low jitter, unlimited (modulo 2/spl pi/) phase shift, and large operating range. The architecture employs a core loop to generate coarsely spaced clocks, which are then used by a peripheral loop to generate the main system clock through phase interpolation. The design of an experimental prototype in a 0.8-/spl mu/m CMOS technology is described. The prototype achieves an operating range of 80 kHz-400 MHz. At 250 MHz, its peak-to-peak jitter with quiescent supply is 68 ps, and its jitter supply sensitivity is 0.4 ps/mV.
508 citations
Related Topics (5)
Performance Metrics
| Year | Papers |
|---|---|
| 2025 | 4 |
| 2024 | 10 |
| 2023 | 12 |
| 2022 | 23 |
| 2021 | 20 |
| 2020 | 40 |