Topic
Delay line memory
About: Delay line memory is a research topic. Over the lifetime, 34 publications have been published within this topic receiving 224 citations.
Papers
TL;DR: A model for digital synchronous delay line memory (DSDLM) is given, yielding limitations on the maximum number of bits that can be reliably stored for a given change in delay medium temperature and amount of medium dispersion.
Abstract: A model for digital synchronous delay line memory (DSDLM) is given, yielding limitations on the maximum number of bits that can be reliably stored for a given change in delay medium temperature and amount of medium dispersion. More than 22 million bits can be stored when single-mode optical fiber is used as the medium, but only if operated at the wavelength of minimum dispersion and by limiting thermal fluctuations to within 0.002 degrees C. A DSDLM is being constructed using such fiber, along with lithium niobate directional couplers as the switching elements. Signal regeneration errors, switch crosstalk, and polarization losses are negligible for the implementation. With a modulation frequency of 100 MHz, a single-line 2000-bit memory can be reliably operated without thermal compensation given a temperature fluctuation of <80 degrees C.
46 citations
1 Aug 1949
TL;DR: The memory system described makes possible a significant increase in the over-all speed of an electronic computer.
Abstract: A mercury delay line memory system for electronic computers, capable of operating at pulse repetition rates of several megacycles per second, has been developed. The high repetition rate results in a saving in space and a reduction in access time. Numerous improvements in techniques have made the high repetition rate possible. The use of the pulse envelope system of representing data has effectively doubled the possible pulse rate; the use of crystal gating circuits has made possible the control of signals at high pulse rates; and a multichannel memory using a single pool of mercury has simplified the mechanical construction, reduced the size, and made temperature control much easier. The memory system described makes possible a significant increase in the over-all speed of an electronic computer.
34 citations
TL;DR: The degradation of data in the memoryloop as the phase error tolerance is exceeded by a small amount is studied through the temperature dependence of the memory loop and the results of these experiments support the feasibility of a 100-MHz 128 x 16 bit memory.
Abstract: The construction and operation of a 50-MHz 64 × 16 bit fiber-optic bit-serial delay-line memory is described. It consists of LiNbO3 directional coupler switches, fused-fiber couplers, and a 4.17-km fiber loop. It is a subsystem of a bit-serial optical computer under construction by our group. We discuss delay and clock source stability requirements for the long delay line in the face of a limited phase error tolerance. The reliability testing of the memory subsystem is described. The degradation of data in the memory loop as the phase error tolerance is exceeded by a small amount is studied through the temperature dependence of the memory loop. Data are presented for the memory-loop stability with respect to temperature variations. The memory subsystem design and construction is presented. The results of these experiments support the feasibility of a 100-MHz 128 × 16 bit memory.
23 citations
TL;DR: In this paper, a tunable all-optical delay line for a vertical-cavity surface-emitting laser with a saturable absorber was proposed. But the authors only considered the ratio of the carrier lifetimes in the amplifier and in the absorber.
Abstract: Cavity soliton lasers in a vertical-cavity surface-emitting laser with a saturable absorber can spontaneously move provided that a proper ratio of the carrier lifetimes in the amplifier and in the absorber is considered. Use is made of this fact to propose a scheme based on which a tunable all-optical delay line can be demonstrated. This easy-to-realize delay device exhibits high delay range, a very good delay resolution, and a wide extent of available data bandwidth. Also it is shown that the ratio of delay time to pulse duration (fractional delay) can be as large as 2300.
16 citations
Related Topics (5)
Performance Metrics
| Year | Papers |
|---|---|
| 2015 | 2 |
| 2014 | 1 |
| 2005 | 1 |
| 2003 | 1 |
| 1999 | 3 |
| 1997 | 1 |