TL;DR: Experimental, results are presented to demonstrate the accuracy and potential of Xception in the evaluation of the dependability properties of the complex computer systems available nowadays.
Abstract: An important step in the development of dependable systems is the validation of their fault tolerance properties Fault injection has been widely used for this purpose, however with the rapid increase in processor complexity, traditional techniques are also increasingly more difficult to apply This paper presents a new software-implemented fault injection and monitoring environment, called Xception, which is targeted at modern and complex processors Xception uses the advanced debugging and performance monitoring features existing in most modern processors to inject quite realistic faults by software, and to monitor the activation of the faults and their impact on the target system behavior in detail Faults are injected with minimum interference with the target application The target application is not modified, no software traps are inserted, and it is not necessary to execute the target application in special trace mode (the application is executed at full speed) Xception provides a comprehensive set of fault triggers, including spatial and temporal fault triggers, and triggers related to the manipulation of data in memory Faults injected by Xception can affect any process running on the target system (including the kernel), and it is possible to inject faults in applications for which the source code is not available Experimental, results are presented to demonstrate the accuracy and potential of Xception in the evaluation of the dependability properties of the complex computer systems available nowadays
TL;DR: In this article, a hardware-oriented verification-specific object-oriented programming language is used to construct and customize verification tests, and a test generator module automatically creates verification tests from a functional description.
Abstract: A method and apparatus are provided for functionally verifying an integrated circuit design. A hardware-oriented verification-specific object-oriented programming language is used to construct and customize verification tests. The language is extensible, and shaped to provide elements for stimulating and observing hardware device models. The invention is platform and simulator-independent, and is adapted for integration with Verilog, VHDL, and C functions. A modular system environment ensures interaction with any simulator through a unified system interface that supports multiple external types. A test generator module automatically creates verification tests from a functional description. A test suite can include any combination of statically and dynamically-generated tests. Directed generation constrains generated tests to specific functionalities. Test parameters are varied at any point during generation and random stability is supported. A checking module can perform any combination of static and dynamic checks. Incremental testing permits gradual development of test suites throughout the design development process. Customized reports of functional coverage statistics and cross coverage reports can be generated. A graphical user interface facilitates the debugging process. High-Level Verification Automation facilities, such as the ability to split and layer architecture and test files, are supported. Both verification environments and test suites can be reused.
TL;DR: An active debugging environment for debugging a virtual application that contains program language code from multiple compiled and/or interpreted programming languages is described in this paper, where a process debug manager and a machine debug manager act as an interface between the language engine specific programming language details and the debug user interface.
Abstract: An active debugging environment for debugging a virtual application that contains program language code from multiple compiled and/or interpreted programming languages. The active debugging environment is language neutral and host neutral, where the host is a standard content centric script host with language engines for each of the multiple compiled and/or interpreted programming languages represented in the virtual application. The active debugging environment user interface can be of any debug tool interface design. The language neutral and host neutral active debugging environment is facilitated by a process debug manager that catalogs and manages application specific components, and a machine debug manager that catalogs and manages the various applications that comprise a virtual application being run by the script host. The process debug manager and the machine debug manager act as an interface between the language engine specific programming language details and the debug user interface.
TL;DR: This thesis presents a technique for debugging lazy functional programs declaratively and an efficient implementation of a declarative debugger for a large subset of Haskell, believed to be the first implementation of such a debugger which is sufficiently efficient to be useful in practice.
Abstract: Lazy functional languages are declarative and allow the programmer to write programs where operational issues such as the evaluation order are left implicit. It is desirable to maintain a declarative view also during debugging so as to avoid burdening the programmer with operational details, for example concerning the actual evaluation order which tends to be difficult to follow. Conventional debugging techniques focus on the operational behaviour of a program and thus do not constitute a suitable foundation for a general-purpose debugger for lazy functional languages. Yet, the only readily available, general-purpose debugging tools for this class of languages are simple, operational tracers.This thesis presents a technique for debugging lazy functional programs declaratively and an efficient implementation of a declarative debugger for a large subset of Haskell. As far as we know, this is the first implementation of such a debugger which is sufficiently efficient to be useful in practice. Our approach is to construct a declarative trace which hides the operational details, and then use this as the input to a declarative (in our case algorithmic) debugger.The main contributions of this thesis are:A basis for declarative debugging of lazy functional programs is developed in the form of a trace which hides operational details. We call this kind of trace the Evaluation Dependence Tree (EDT).We show how to construct EDTs efficiently in the context of implementations of lazy functional languages based on graph reduction. Our implementation shows that the time penalty for tracing is modest, and that the space cost can be kept below a user definable limit by storing one portion of the EDT at a time.Techniques for reducing the size of the EDT are developed based on declaring modules to be trusted and designating certain functions as starting-points for tracing.We show how to support source-level debugging within our framework. A large subset of Haskell is handled, including list comprehensions.Language implementations are discussed from a debugging perspective, in particular what kind of support a debugger needs from the compiler and the run-time system.We present a working reference implementation consisting of a compiler for a large subset of Haskell and an algorithmic debugger. The compiler generates fairly good code, also when a program is compiled for debugging, and the resource consumption during debugging is modest. The system thus demonstrates the feasibility of our approach.
TL;DR: In this article, a distributed, compiler-oriented database with operating modes including parallel compilation, parallel simulation and parallel execution of computer programs and hardware models is presented, in order to efficiently support parallel database clients such as a source code analyser, an elaborator, an optimizer, mapping and scheduling, code generation, linking/loading, execution/simulation, debugging, profiling, user interface and a file interface.
Abstract: A distributed, compiler-oriented database is disclosed with operating modes including parallel compilation, parallel simulation and parallel execution of computer programs and hardware models. The invention utilizes a hardware apparatus consisting of shared memory multiprocessors, optionally augmented by processors with re-configurable logic execution pipelines or independently scheduled re-configurable logic blocks and a software database apparatus, manifest in the hardware apparatus, in order to efficiently support parallel database clients such as a source code analyser, an elaborator, an optimizer, mapping and scheduling, code generation, linking/loading, execution/simulation, debugging, profiling, user interface and a file interface.
TL;DR: The performance of SimICS/sun4m is sufficient to run realistic workloads, such as the database benchmark TPC-D, scaling factor 1/100, or an interactive network application such as Mozilla, and the slowdown in relation to native hardware is in the range of 25 to 75 (measured using SPECint95).
Abstract: System level simulators allow computer architects and system software designers to recreate an accurate and complete replica of the program behavior of a target system, regardless of the availability, existence, or instrumentation support of such a system. Applications include evaluation of architectural design alternatives as well as software engineering tasks such as traditional debugging and performance tuning.
We present an implementation of a simulator acting as a virtual workstation fully compatible with the sun4m architecture from Sun Microsystems. Built using the system-level SPARC V8 simulator SimICS, SimICS/sun4m models one or more SPARC V8 processors, supports user-developed modules for data cache and instruction cache simulation and execution profiling of all code, and provides a symbolic and performance debugging environment for operating systems.
SimICS/sun4m can boot unmodified operating systems, including Linux 2.0.30 and Solaris 2.6, directly from snapshots of disk partitions. To support essentially arbitrary code, we implemented binary-compatible simulators for several devices, including SCSI, console, interrupt, timers, EEPROM, and Ethernet. The Ethernet simulation hooks into the host and allows the virtual workstation to appear on the local network with full services available (NFS, NIS, rsh, etc). Ethernet and console traffic can be recorded for future playback.
The performance of SimICS/sun4m is sufficient to run realistic workloads, such as the database benchmark TPC-D, scaling factor 1/100, or an interactive network application such as Mozilla. The slowdown in relation to native hardware is in the range of 25 to 75 (measured using SPECint95). We also demonstrate some applications, including modeling an 8-processor sun4m version (which does not exist), modeling future memory hierarchies, and debugging an operating system.
TL;DR: This work presents an SDG for object oriented software that is more precise than previous representations and is more efficient to construct than previous approaches and introduces the concept of object slicing and an algorithm to implement this concept.
Abstract: We present an SDG for object oriented software that is more precise than previous representations and is more efficient to construct than previous approaches. The new SDG distinguishes data members for different objects, provides a way to represent object parameters, represents the effects of polymorphism on parameters and parameter bindings, represents incomplete classes efficiently, and provides a way to represent class libraries. Based on this system dependence graph, we introduce the concept of object slicing and an algorithm to implement this concept. Object slicing enables the user to inspect the statements in the slice, object-by-object, and is helpful for debugging and impact analysis.
TL;DR: In this article, a technique, system, and computer program for enabling multiple virtual machines to execute on a single server, using virtual machine pooling, is described, which will result in a more scalable network environment, increasing the processing capacity of the server and decreasing the amount of time a particular request waits before being processed.
Abstract: A technique, system, and computer program for enabling multiple virtual machines to execute on a single server, using virtual machine pooling. This will result in a more scalable network environment, increasing the processing capacity of the server and decreasing the amount of time a particular request waits before being processed. Further, the integrity of an application's data will be protected from inadvertent overwriting by another application, because each application can be running in a separate virtual machine. Garbage collection, crashes, and hangs will no longer temporarily or completely halt a server: when one virtual machine halts, others can continue executing. Multiple environments can now execute on a single server, including different versions of virtual machines, increasing the mix of servlets that can be supported. Further, debugging can now occur concurrently with normal application execution, by isolating the debugging function to a specific virtual machine.
TL;DR: In this article, a system for building communities of collaborative software agents is presented, where each software agent has data concerning its relationship(s) with other agents of the community and a visualiser is provided for debugging the community.
Abstract: A community of collaborative software agents works together in a domain to provide functionality such as provision of communications services or control of a chemical process. A system is provided for building such communities of collaborative software agents. Each software agent has data concerning its relationship(s) with other agents of the community. A visualiser is provided for debugging the community which offers several partial views of the communications between and within agents, organised according to the relationships between agents. By using multiple partial views, such as messages between selected agents and job status reports within single agents, the visualiser is capable of particularly effective debugging.
TL;DR: In this paper, the authors present an object-tracing tool for tracing software entities in distributed computing environments by using a network management entity to keep track of the location of the entities in the system and using a library of modules that can be inherited to provide tracing capabilities.
Abstract: The invention relates to a process and apparatus for tracing software entities, more particularly a tracing tool providing tracing capabilities to entities in an application. The object-tracing tool provides software components to allow tracing the execution of an application. Tracing software entities is important for software developers to permit the quick localization of errors and hence facilitate the debugging process. It is also useful for the software user who wishes to view the control flow and perhaps add some modifications to the software. Traditionally, software-tracing tools have been confined to single node systems where all the components of an application run on a single machine. The novel tracing tool presented in this application provides a method and an apparatus for tracing software entities in a distributed computing environment. This is done by using a network management entity to keep track of the location of the entities in the system and by using a library of modules that can be inherited to provide tracing capabilities. It also uses a log file to allow the program developer or user to examine the flow, the occurrence of events during a trace and the values of designated attributes. The invention also provides a computer readable storage medium containing a program element to direct a processor of a computer to implement the software tracing process.
TL;DR: In this article, a data processor is provided with an embedded debugger, which allows the internal registers used during execution of a user program to be examined and debug operation can be initiated via debug instruction which replaces an existing instruction in the user code.
Abstract: A data processor is provided with an embedded debugger. The debugging function is provided by the execution of a debugging program which is stored in reserved, non-volatile memory which is internal to the data processor. During the debug mode, the data processor allows the internal registers used during execution of a user program to be examined. Debug operation can be initiated via debug instruction which replaces an existing instruction in the user code, the replaced instruction being held in a special purpose register such that it can be executed on return from the debug mode. Single step operation of the data processor can be performed in debug mode and data and instructions can be exchanged with the data processor in debug mode, optionally via a single pin so as not to sacrifice any user resources.
TL;DR: In this article, the authors present a method, apparatus, and article of manufacture for providing a programming development environment that supports the development of internet and intranet applications, including a debug control embedded in a debug proxy file.
Abstract: A method, apparatus, and article of manufacture for providing a programming development environment that supports the development of internet and intranet applications. The present invention describes a method, apparatus, and article of manufacture for remotely debugging internet applications. A debug control embedded in a debug proxy file is used to establish a debug session with a development client and to transmit the application to the user computer's browser, so as to present data in controls therein.
TL;DR: In this article, a microprocessor having memory arrays, a debug block, and one or more built-in-self-test (BIST) engines is disclosed, where the debug block is capable of driving control information out onto a state machine output bus in response to an event and the control information can be selectively used to control signature analysis or recording elements of the microprocessor.
Abstract: A method and structure facilitates the debugging and test coverage capabilities of a microprocessor. A microprocessor having memory arrays, a debug block, and one or more built-in-self-test (BIST) engines is disclosed. The debug block is capable of driving control information out onto a state machine output bus in response to an event and the control information can be selectively used to control signature analysis or recording elements of the microprcessor, such as multiple-input-shift-registers and first-in-first-out devices, that facilitate in the monitoring and debugging of the microprocessor. The signature and recording elements may or may not be contained within the one or more BIST engines and may or may not be used in conjunction with the memory arrays or BIST engine(s) of the microprocessor.
TL;DR: In this paper, a method and apparatus for allowing multiple developers of software applications working in client/server computing network to remotely save, test and debug project files such as web pages is presented.
Abstract: A method and apparatus for allowing multiple developers of software applications working in client/server computing network to remotely save, test and debug project files such as web pages. The client computer is capable of emulating server side operations to allow the developer to locally test changes to project files before they are saved on the server. The client computer maintains an accurate view of the overall project, but without having to locally copy the entire software project, by storing file information relating to the software project including, for example, metadata, link information, and BOT replacements, and/or a directory structure of the files and folders in the software project that mirrors the directory structure of the software project on the server. Various features include providing developers with the ability to check out, modify and debug files concurrently with other developers, and merging changes made by different developers to the same file. Concurrently modified files may be merged by prompting a developer when conflicts arise between the files to be merged.
TL;DR: Why a tightly integrated problem solving environment, such as SCIRun, simplifies the design and debugging phases of computational science applications and how such an environment aids in the scientific discovery process is discussed.
Abstract: SCIRun is a scientific programming environment that allows the interactive construction, debugging, and steering of large-scale scientific computations. We review related systems and introduce a taxonomy that explores different computational steering solutions. Considering these approaches, we discuss why a tightly integrated problem solving environment, such as SCIRun, simplifies the design and debugging phases of computational science applications and how such an environment aids in the scientific discovery process.
TL;DR: In this paper, a parallel processor with integrated debugging capabilities is described, which includes a pipelined processing engine, having an array of processing element complex stages, and input and output header buffers.
Abstract: A parallel processor is provided that includes integrated debugging capabilities. The processor includes a pipelined processing engine, having an array of processing element complex stages, and input and output header buffers. A debug system is provided that, when triggered, may put some or all of the processing element complexes into a debug mode of operation. When a complex is in debug mode, examination of internal stages of the component circuits of the complex may occur, in order to facilitate debugging of software and hardware errors that may occur during operation of the processor.
TL;DR: In this article, a debugging information program can be hooked into a decompiler to generate the debugging information and modify the source code output by the decompiler, such as inserting or deleting source statements, generating line numbers for source lines, or assigning variable names to variables encountered in the executable code.
Abstract: A debugging system according to the present invention includes a decompiler that provides information to a table generator, which generates a line number map and a symbol table, each of which corresponds to an executable file being decompiled. In a specific embodiment, hooks into specific operations performed by the decompiler trigger the table generator operation. A debugging information program can be hooked into a decompiler to generate the debugging information and modify the source code output by the decompiler. For example, the program can be hooked into the decompiler to monitor when the decompiler inserts or deletes source statements, generates line numbers for source lines, or assigns variable names to variables encountered in the executable code.
TL;DR: A natural language information retrieval (NLIR) system employing a hash table technique to reduce memory requirements and a proxy process module to improve processing speed on multi-processor platforms is described in this paper.
Abstract: A natural language information retrieval (NLIR) system employing a hash table technique to reduce memory requirements and a proxy process module to improve processing speed on multi-processor platforms. The NLIR system includes a Dynamic Link Library (DLL) search engine annex that implements a number of improvements that allow the preexisting natural language processing (NLP) core code module to operate sufficiently fast in a limited-memory environment. The improvements relate to (1) reducing storage requirements, (2) increasing processing speed, (3) improved operation on multi-processor platforms, and (4) a trouble-shooting mechanism. The NLIR system includes three modes of operation. First, during index processing, the NLIR system prepares documents for NLP searching to create a group of searchable documents. Second, during question processing, the NLIR system receives a natural language question and, for each document in the group of searchable documents, computes a document score connoting the likelihood that the document includes an answer to the natural language question. Third, during debugging, the NLIR system receives trouble-shooting requests and returns diagnostic reports, such as a document trace report and a question trace report.
TL;DR: Why the Java virtual machine is an effective environment for exploiting method-level parallelism, and how method speculation can potentially speed up single-threaded general purpose Java programs are shown.
Abstract: Method speculation of object-oriented programs attempts to exploit method-level parallelism (MLP) by executing sequential method invocations in parallel, while still maintaining correct sequential ordering of data dependencies and memory accesses. In this paper, we show why the Java virtual machine is an effective environment for exploiting method-level parallelism, and demonstrate how method speculation can potentially speed up single-threaded general purpose Java programs. Results from our study show that significant speedups can be achieved on data-parallel applications with minimal programmer and compiler effort. On control-flow dependent programs, moderate speedups have been achieved, suggesting more significant performance improvements on these types of programs may come from more careful analysis or re-coding of the application. For both classes of applications, we discover performance debugging drastically improves speedups by eliminating or minimizing dependencies that limit the effectiveness of method speculation.
TL;DR: In this paper, the authors present an interactive system for debugging programs in which a persistent data base system responds to update queries containing debugging information from a debugging information source and to read queries on the debug information from an interactive interface.
Abstract: An interactive system for debugging programs in which a persistent data base system responds to update queries containing debugging information from a debugging information source and to read queries on the debugging information from an interactive interface. The interactive interface produces the read queries in response to inputs from users and formats the results of the read queries as required by the user. One source of inputs is a standard Web browser for which the interactive interface functions as a Web server. The system also includes a command channel by which the source of debugging information receives commands from the interactive interface. In one embodiment, the command channel is implemented in the data base. In a disclosed implementation, the source of debugging information provides memory debugging information. Also disclosed are techniques for using an automatic memory management system to reduce memory fragmentation and heap footprint size.
TL;DR: Disclosed as discussed by the authors is a system for debugging a computer program, where a user indicates a specified breakpoint type, such as a program statement, variable reference, command, etc. The program, including program statements, is then compiled.
Abstract: Disclosed is a system for debugging a computer program. A user indicates a specified breakpoint type, such as a program statement, variable reference, command, etc. The program, including program statements, is then compiled. During compilation, the compiler locates statements in the program corresponding to the breakpoint types and generates a function call into the program at instances in the program of statements corresponding to the user specified breakpoint types. During a debugging phase, a debugger may execute an executable version of the program, including the function calls. Upon processing the function calls, the debugger may stop execution of the program and pass control to the user to perform debugging operations.
TL;DR: In this article, a scheduler is utilized to schedule the threads in a queue, and the threads are divided up into instruction slices each consisting of a predetermined number of instructions, and then the scheduler executes each instruction slice.
Abstract: A computer system which permits deterministic and preemptive scheduling of threads in a software application. In one embodiment, a scheduler is utilized to schedule the threads in a queue. Once the threads are scheduled, they are divided up into instruction slices each consisting of a predetermined number of instructions. The scheduler executes each instruction slice. An instruction counter is utilized to keep track of the number of instructions executed. The thread is permitted to run the instruction slice until the predetermined number of instructions has been executed. Alternatively, the thread stops if it is blocked while waiting for an input, for example. The next thread is then executed for the same number of instructions. This process permits for the efficient debugging of software which utilizes traditional cyclic debugging.
TL;DR: In this article, a software development tool permits capture, modification and recording of transactional messages that are transmitted between a client (26) and a server (28) in a computer network.
Abstract: A software development tool (10) permits capture, modification and recording of transactional messages that are transmitted between a client (26) and a server (28) in a computer network. A proxy is employed to capture messages such as requests and responses that are in transit between the client (26) and the server (28). The captured requests and responses can be displayed and modified before being retransmitted via the proxy. Further, transaction records can be selectively provided to at least one software application (46) for analysis.
TL;DR: Software techniques for increasing design visibility while reducing tracing overhead in simulation, and achieving 100% visibility in emulation without reducing speed or compromising depth are discussed.
Abstract: Cycle simulators, in-circuit emulators, and hardware accelerators have made it possible to rapidly model the functionality of large digital designs. But these techniques provide limited visibility of internal design nodes, making debugging hard. Simulators run slowly when all nodes are traced. Emulators provide full visibility only with limited depth, or with greatly reduced speed. This paper discusses software techniques for increasing design visibility while reducing tracing overhead in simulation, and achieving 100% visibility in emulation without reducing speed or compromising depth.
TL;DR: An image processing system built around PADDI-2, a custom 48 node MIMD parallel DSP, which supports a multiprocessor system under development (VGI-1), with implementation dependencies isolated in layered encapsulations.
Abstract: We have integrated an image processing system built around PADDI-2, a custom 48 node MIMD parallel DSP. The system includes image processing algorithms, a graphical SFG tool, a simulator, routing tools, compilers, hardware configuration and debugging tools, application development libraries, and software implementations for hardware verification. The system board, connected to a SPARCstation via a custom Sbus controller, contains 384 processors in 8 VLSI chips. The software environment supports a multiprocessor system under development (VGI-1). The software tools and libraries are modular, with implementation dependencies isolated in layered encapsulations.
TL;DR: In this article, a method and system for emulating network latency, packet corruption, packet shuffling, packet loss and network congestion is introduced so that network connected multi-computer software systems can be tested and debugged in a cost effective and efficient manner.
Abstract: A method and system for emulating network latency, packet corruption, packet shuffling, packet loss and network congestion is introduced so that network connected multi-computer software systems can be tested and debugged in a cost effective and efficient manner. This network emulator requires no changes to the software being tested and requires only modifications to the MAC to IP mapping tables of the computers running the software to be tested. IT requires no modification to the communication stacks of the computers involved. The changes to these tables cause packets to be redirected to an emulator host computer where they can be delayed, deleted, corrupted or shuffled prior to delivery to their final destination.
TL;DR: Montana as discussed by the authors is an extensible integrated programming environment for C++ that supports incremental compilation and linking, a persistent code cache called a CodeStore, and a set of programming interfaces to the CodeStore for tool writers.
Abstract: Montana is an open, extensible integrated programming environment for C++ that supports incremental compilation and linking, a persistent code cache called a CodeStore, and a set of programming interfaces to the CodeStore for tool writers CodeStore serves as a central source of information for compiling, browsing, and debugging CodeStore contains information about both the static and dynamic structure of the compiled program This information spans files, macros, declarations, function bodies, templates and their instantiations, program fragment dependencies, linker relocation information, and debugging informationMontana allows the compilation process to be extended and modified [11] Montana has been used as the basis of a number of tools [1,7], and is also used as the infrastructure of a production compiler, IBM's Visual Age C++ 40 [8]
TL;DR: The modifications to the Glasgow Haskell compiler based on detailed cost semantics and an efficient implementation scheme are discussed and the results of using this new profiling tool in the analysis of a number of Haskell programs are presented.
Abstract: The LOLITA natural language processor is an example of one of the ever-increasing number of large-scale systems written entirely in a functional programming language. The system consists of over 47,000 lines of Haskell code (excluding comments) and is able to perform a wide range of tasks such as semantic and pragmatic analysis of text, information extraction and query analysis. The efficiency of such a system is critical; interactive tasks (such as query analysis) must ensure that the user is not inconvenienced by long pauses, and batch mode tasks (such as information extraction) must ensure that an adequate throughput can be achieved. For the past three years the profiling tools supplied with GHC and HBC have been used to analyse and reason about the complexity of the LOLITA system. There have been good results, however experience has shown that in a large system the profiling life-cycle is often too long to make detailed analysis possible, and the results are often misleading. In response to these problems a profiler has been developed which allows the complete set of program costs to be recorded in so-called cost-centre stacks. These program costs are then analysed using a post-processing tool to allow the developer to explore the costs of the program in ways that are either not possible with existing tools or would require repeated compilations and executions of the program. The modifications to the Glasgow Haskell compiler based on detailed cost semantics and an efficient implementation scheme are discussed. The results of using this new profiling tool in the analysis of a number of Haskell programs are also presented. The overheads of the scheme are discussed and the benefits of this new system are considered. An outline is also given of how this approach can be modified to assist with the tracing and debugging of programs.
TL;DR: A framework that provides assurance on the correctness of program execution at run-time based on the Monitoring and Checking (MaC) architecture is described, and complements the two traditional approaches for ensuring that a system is correct, namely static analysis and testing.
Abstract: Computer systems are often monitored for performance evaluation and enhancement, debugging and testing, control or to check for the correctness of the system. Recently, the problem of designing monitors to check for the correctness of system implementation has received increased attention from the research community. Traditionally, verification has been used to increase the confidence that a system will be correct by making sure that a design specification is correct. However, even if a design has been formally verified, it still does not ensure the correctness of an implementation of the design. This is because the implementation often is much more detailed, and may not strictly follow the formal design. So, there is possibility for introduction of errors into an implementation of a design that has been verified. One way that people have traditionally tried to overcome this gap between the design and the implementation has been to test the implementation's behavior on a pre-determined set of input sequences. This approach, however, fails to provide guarantees about the correctness of the implementation on all possible input sequences. Consequently, when a system is running, it is hard to guarantee whether the current execution of the system is correct or not using the two traditional methods. Therefore, the approach of continuously monitoring a running system has received much attention, as it attempts to overcome the difficulties encountered by the two traditional methods for checking the correctness of the current execution of the system. We describe a framework that provides assurance on the correctness of program execution at run-time. This approach is based on the Monitoring and Checking (MaC) architecture, and complements the two traditional approaches for ensuring that a system is correct, namely static analysis and testing. Unlike these approaches which try to ensure that all possible executions of the system are correct, this approach ensures only that the current execution of the system is correct. The MaC architecture consists of three components: filter, event recognizer, and runtime checker. The filter extracts low-level information, in the form of values of program variables, from the instrumented system code, and sends it to the event recognizer. From this low-level information, the event recognizer detects the occurrence of abstract events, and informs the run-time checker about these. The run-time checker then, based on the events, checks the conformance of the behavior of the system on the current execution, to the formal requirement specification for the system. Acknowledgment. This research was supported in part by NSF CCR-9415346, NSF CCR9619910, AFOSR F49620-95-1-0508, ARO DAAG55-98-1-0393, ARO DAAG55-98-1-0466, and ONR N00014-97-1-0505 (MURI). The current address of Ben-Abdallah is at Department of d’Informatique, Universite de Sfax, Tunisia.
TL;DR: In this article, the authors present an approach to reduce application size by eliminating unreachable methods by determining the methods in an application A that may be called from another reachable method in A, or from within a class library L without analyzing the classes in L.
Abstract: The present invention analyzes an application A and computes a set reachable methods in A by determining the methods in A that may be called from another reachable method in A, or from within a class library L used by A without analyzing the classes in L The invention may be used as an optimization to reduce application size by eliminating unreachable methods In the alternative, the invention may be used as a basis for optimizations that reduce execution time (eg, by means of call devirtualization), and as a basis for tools for program understanding and debugging