Abstract: We review the field of result-checking, discussing simple checkers and self-correctors. We argue that such checkers could profitably be incorporated in software as an aid to efficient debugging and enhanced reliability. We consider how to modify traditional checking methodologies to make them more appropriate for use in real-time, real-number computer systems. In particular, we suggest that checkers should be allowed to use stored randomness: that is, that they should be allowed to generate, preprocess, and store random bits prior to run-time, and then to use this information repeatedly in a series of run-time checks. In a case study of checking a general real-number linear transformation (e.g., a Fourier Transform), we present a simple checker which uses stored randomness, and a self-corrector which is particularly efficient if stored randomness is employed.

Abstract: A parallel multithreaded program that is ostensibly deterministic may nevertheless behave nondeterministically due to bugs in the code. These bugs are called determinacy races, and they result when one thread updates a location in shared memory while another thread is concurrently accessing the location. We have implemented a provably efficient determinacy-race detector for Cilk, an algorithmic multithreaded programming language. If a Cilk program is run on a given input data set, our debugging tool, which we call the ``Nondeterminator,'' either determines at least one location in the program that is subject to a determinacy race, or else it certifies that the program is race free when run on the data set.

Abstract: Program slicing is a technique for determining the set of statements of a program that potentially affect the value of a variable at some point in the program. Intra and interprocedural slicing of high level languages has greatly been studied in the literature; both static and dynamic techniques have been used to aid in the debugging, maintenance, parallelization, program integration, and dataflow testing of programs. We explain how to apply conventional intraprocedural static analysis to binary executables for the purposes of static analysis of machine code and assembly code, such as debugging code and determining the instructions that affect an indexed jump or an indirect call on a register. This analysis is useful in the decoding of machine instructions phase of reverse engineering tools of binary executables, such as binary translators, disassemblers, binary profilers and binary debuggers

Abstract: A system coordinates software development activities with planning documents (e.g. Gantt charts). Planning documents are created and/or edited to reflect the structure of underlying code by assigning module and procedures to task lines. Further enhancements of the invention provide mechanism for manager to know where coder(s) are stuck or ignoring code. A monitor process on the developer's computer identifies exception generating code, and integrating bug lists from disparate sources into one unified planning document. The information used to generate the planning document is used to provide a mechanism of transferring that links bugs, code, and intent in one package. The system is extended to provide automated defect detection and correction, particularly in the areas of run-time exceptions, endless loops, control flow errors, data errors, and errors caused by breaking working code with later edits. The combination of the invention's code driven management paradigm and automated debugging mechanism provides an enhanced mechanism for sharing knowledge among developers.

Abstract: A processor-based device incorporating a software debug port that utilizes a JTAG or similar standardized interface, thereby providing a software debug communication mechanism that does not require a special bond-out package. In one embodiment of the invention, only standard JTAG pins are used for communications between a host platform and a target system incorporating a target processor. In another embodiment of the invention, the software debug port of the target processor is augmented for higher-speed access via optional sideband signals. When used in conjunction with an on-chip trace cache, the software debug port provides trace information for reconstructing instruction execution flow on the processor and is also capable of examining register contents without halting processor operation. The software debug port alleviates many of the packaging and clock synchronization problems confronting existing debug solutions.

Abstract: To illustrate these ideas, we present three visualization approaches we have explored—algorithm animation, typographic source code presentation, and interactive auralization for debugging—demonstrating the richness of software visualization media and portraying design trade-offs inherent in their use. We use a 30-minute film (designed to teach nine sorting algorithms) to demonstrate the power of algorithm animation. We show how the design and typesetting of computer program source text can enhance the program’s readability. And we show how a programming environment we created—LogoMedia—is useful for the interactive construction of visualizations during program creation and debugging. Software Vi for Debugging

Abstract: A development system having a monitor/profiler tool for monitoring functions in natively compiled software programs is described. According to the present invention, the monitor/profiler tool is constructed to work directly on a natively compiled software application which only have debugging info. Unlike prior approaches, the monitor/profiler tool does not require a special compile or link phase for the application under exam. The tool can monitor any function in software application which has debug info, thus relieving program developers from the burden of maintaining two ways of building an application. The developer can simply use the same executable for both development and function analysis.

Abstract: Object relationships in modem software systems are becoming increasingly numerous and complex. Programmers who try to find violations of such relationships need new tools that allow them to explore objects in a large system more efficiently. Many existing debuggers present only a low-level, one-object-at-a-time view of objects and their relationships. We propose a new solution to overcome these problems: query-based debugging. The implementation of the query-based debugger described here offers programmers an effective query tool that allows efficient searching of large object spaces and quick verification of complex relationships. Even for programs that have large numbers of objects, the debugger achieves interactive response times for common queries by using a combination of fast searching primitives, query optimization, and incremental result delivery.

Abstract: A dynamic program slice is an executable part of a program whose behavior is identical, for the same program input, to that of the original program with respect to a variable(s) of interest at some execution position. In the existing dynamic slicing tools dynamic slices are represented in a textual form, i.e., a dynamic slice is displayed to programmers in the form of highlighted statements or in the form of a subprogram. Although dynamic slicing does narrow the size of the program, it is still up to the programmer to analyze the text of a dynamic slice and identify a faulty part in the program. The textual representation of a dynamic slice does not provide much guidance in program debugging and understanding of program behavior, which frequently is a major factor in efficient debugging. During dynamic slice computation different types of information are computed and then discarded after computation of the dynamic slice. In this paper we propose new dynamic slicing related features that exploit this information to improve the process of program debugging. These features were implemented in our dynamic slicing tool that can be used for program debugging.

Abstract: A system and method for debugging and tuning a process control network having distributed control functions implemented by a set of field devices communicatively linked over a bus includes an operational scheduler that schedules the execution of each of a number of process control functions and communication functions performed by the field devices to define a process control scheme and an indicator that indicates one or more process control scheme locations at which the process control scheme is to be automatically or conditionally interrupted to thereby enable debugging and/or tuning of the process control network. A controller interrupts execution of the process control scheme at the indicated flow locations, communicates process data to a user to display the current or a past state of the process to a user and waits for user input before continuing with operation of the process control scheme. In a tuning mode, the controller delivers data pertaining to a process parameter to a tuning device or to a user which determines a new tuning parameter, such as a gain, to be used within the process control scheme based on the process parameter data.

Abstract: The apparatus (100) for debugging a digital processor (130) on an integrated circuit (110) contains a debugger monitor (125) embedded on the integrated circuit that also contains the digital processor. The debugger monitor is preferably connected between the processor and IC logic (120). The debugger monitor is connected, preferably by a serial connection, to an external host computer (105) for controlling the debugging. The debugger monitor contains a virtual monitor controller (405) and a number of storage devices to store data, instruction, status and mode information. A method is disclosed by which an instruction fetch from the digital processor is intercepted, instructions are downloaded from the host processor and the digital processor is operated with the downloaded instructions. Preferably the connection between host and integrated circuit is over a JTAG boundary scan standard interface and tap controller.

Abstract: To provide high-level graphical support for PVM (Parallel Virtual Machine) based program development, a complex programming environment (GRADE) is being developed. GRADE currently provides tools to construct, execute, debug, monitor and visualize message-passing parallel programs. It offers a high-level graphical programming abstraction mechanism to construct parallel applications by introducing a new graphical language called GRAPNEL. GRADE also provides the programmer with the same graphical user interface during the program design and debugging stages. A distributed debugging engine (DDBG) assists the user in debugging GRAPNEL programs on distributed memory computer architectures. Tape/PVM and PROVE support the performance monitoring and visualization of parallel programs developed in the GRADE environment.

Abstract: A debugging apparatus is disclosed which verifies a program to be embedded into a target machine by running the program in an environment which is one or the target machine, an emulator, and a simulator. Each environment includes operation state information of the program and inputs and outputs the operation state information in a form unique to the environment. The debugging apparatus includes; target environment storing unit for storing an identification name of the target environment; receiving unit for receiving a command from an operator; instruction detecting unit for detecting a certain instruction in the command; specifying unit for, when the certain instruction is detected, specifying a target environment specified by the identification name as a source target environment and for specifying any of the rest of the environments as a destination target environment; reading unit for reading operation state information from the source target environment; converting unit for converting the operation state information into operation state information written in a form unique to the destination target environment; setting unit for setting the converted operation state information in the destination target environment; and operation resuming unit for resuming the operation of the program in the destination target environment.

Abstract: Lazy functional languages are declarative and allow the programmer to write programs where operational issues such as the evaluation order are left implicit. This should be reflected in the design of debuggers for such languages to avoid burdening the programmer with operational details, e.g. concerning the actual evaluation order. Conventional debugging techniques tend to focus too much on operational aspects to be suitable in this context. A record of the execution that only captures the declarative aspects of the execution, leaving out operational details, would be a viable basis for debugging lazy functional programs. Various declarative debugging tools could then be developed on top of such records. In this paper we propose a structure which we call the Evaluation Dependence Tree (EDT) for this purpose, and we describe two different construction methods. Performance problems are discussed along with possible solutions.

Abstract: PROBLEM TO BE SOLVED: To provide a data processing system on an integrated circuit equipped with a microprocessor and a peripheral device together with an emulation unit for enabling the debug and emulation of integrated circuit at the time of connection to an external test system. SOLUTION: A microprocessor 1 has fetch/decode units 10a-10c and an instruction execution pipeline provided with plural execution stages related to the unit of function execution. Since the pipeline of microprocessor 1 is not protected, the waiting time of access to a data memory 22 and register files 20 (20a and 20b) can be utilized by a system program code stored in an instruction storage device 23. An emulation unit 50 performs operation through a method for avoiding any state such as the generation of unrelated operation to affect the memories 22-23 and peripheral devices 60-61 during emulation.

Abstract: Conventional software engineering tends to focus on a small part of the software life cycle: the design and implementation of a product. The bulk of the lifetime cost is in the maintenance phase, where one must live with the product previously developed. Presently, we have little theory and fewer tools to help us manage the maintenance activity. We contend that a fundamental cause of the difficulty is the failure to preserve design information. This results from an over preoccupation with the synthesis and maintenance of code. We offer an alternative paradigm: make the design the central focus of the construction process-get code as a byproduct; make the design the central focus of the maintenance process-preserve revised designs and get code as a byproduct. A transformational scheme for accomplishing this is presented. We call it the Design Maintenance System. The programming roles change radically from coding instances for ill defined specifications to specifiers of functionality and (compiler like) implementation methods. Specification and implementation method debugging would then become prominent activities. The design scheme and change management procedures are illustrated with a simple data processing application. We sketch an ongoing implementation

Abstract: Program slicing is Q technique for determining the set of statements of Q program that potentially affect the value of a variable at some point in the program. Intra and interprocedural slicing of high-level languages has greatly been studied in the literature; both static and dynamic techniques have been used to aid in the debugging, maintenance, parallelization, program integration, and dataflow testing of programs. In this paper we explain how to apply conventional intraprocedural static analysis to binary executables, for the purposes of static analysis of machine-code and assembly code, such as debugging code and determining the instructions that affect an indexed jump or an indirect call on Q register. This analysis is useful in the decoding of machine instructions phase of reverse engineering tools of binary executabdes, such QS binary translators, disassemblers, binary profilers and binary debuggers.

Abstract: In a program debugging system for debugging a program having a graphical user interface (GUI), a translator program for translating a source program into a machine language program includes a GUI information output function for extracting information of a GUI parts from the source program and outputting a GUI information relating an operation descriptor describing an operation of the GUI parts, with the GUI parts itself. A debugger includes a break condition setting function for retrieving the source program with reference to the GUI information, to find out the operation descriptor corresponding to the GUI parts designated on a computer display screen, and for setting the break condition for the operation descriptor retrieved. Thus, a trouble or load for a program analysis at the program debugging time is omitted and the debugging procedure is simplified, so that efficiency of the program development and quality of the program developed are elevated.

Abstract: The present invention provides a test and diagnosis system for testing an embedded processor. The test system includes an ASIC having an embedded microprocessor, a debug assist logic unit for monitoring the addresses and data from the embedded microprocessor, a debug kernel and an instruction overlay harness. When the debug assist logic block finds a predetermined set of match conditions, it interrupts the embedded microprocessor and transfers control from the code running on the microprocessor to the debug kernel. The debug kernel is coupled to the debug assist logic unit and responsive to user input, the debug kernel allows the user to trace processor transactions during code execution. A REMAP bit in the ASIC allows remapping of the microprocessor memory into a faster instruction overlay memory, allowing the code to be quickly modified during product debug.

Abstract: A data processing system on an integrated circuit 42 with microprocessor 1 and peripheral devices 60-61 is provided with an emulation unit 50 which allows debugging and emulation of integrated circuit 42 when connected to an external test system 51. Microprocessor 1 has in instruction execution pipeline which has several execution phases which involve fetch/ decode units 10a-c and functional execution units 12, 14, 16 and 18. The pipeline of microprocessor 1 is unprotected so that memory access latency to data memory 22 and register file 20 can be utilized by system program code which is stored in instruction memory 23. Emulation unit 50 provides means for emulating the unprotected pipeline of microprocessor 1 and for rapidly uploading and downloading memories 22-23. Emulation unit 50 operates in a manner to prevent extraneous operations from occurring which could otherwise affect memories 22-23 or peripheral devices 60-61 during emulation.

Abstract: A debugger client/server application comprising a front-end and one or more back-ends, including a Director component which handles most of the initialization and parallel execution control issues and a rp-- client component and rp-- server component which handles most of the distributed execution issues. The Director allows a Debug Engine to be unaware of most of the parallel and distributed aspects of the application. Thus, the Debug Engine can be created by re-using a serial debugger for presenting the state information about the various programs that make up the application.

Abstract: A system for remotely debugging application code on client/server systems. The system comprises a kicker program and a debugging engine installed on the server and a debugging user interface installed on a client machine. When a call is made to the application code on the server machine, the kicker program starts the debugging engine to debug the application code. The kicker program stops the debugging engine when the application code has been stepped through or returns. The debugging engine includes means for remotely starting the debugging user interface installed on the client machine.

Abstract: The Hyper-Geometric Distribution software reliability growth Model (HGDM) was developed to estimate the number of remaining software faults after completing the test/debug phase. An important problem in the software development process is to determine when to stop testing and release the software to the users. In this paper, the cost optimal release policy, which minimizes the total expected software cost, is discussed. The total expected software cost here includes the penalty cost, which should be paid by the manufacturer if the software is delivered after the scheduled delivery time. The underlying software reliability growth model in our approach is the HGDM. Numerical examples are presented for illustration.

Abstract: Visualization has become a critical component of simulation technology. Today we can't imagine doing a simulation without some kind of visualization to help communicate results and get better understanding of a model's behavior. Model build time and debugging have been significantly improved using 2D and 3D animation. The elements of visualization are discussed to help simulation practitioners understand where animation should be employed and how it can improve the process of simulation modeling. The future of visualization in simulation will also be discussed.

Abstract: A data processing system on an integrated circuit 42 with microprocessor 1 and peripheral devices 60-61 is provided with an emulation unit 50 which allows debugging and emulation of integrated circuit 42 when connected to an external test system 51. Microprocessor 1 has in instruction execution pipeline which has several execution phases which involve fetch/ decode units 10a-c and functional execution units 12, 14, 16 and 18. The pipeline of microprocessor 1 is unprotected so that memory access latency to data memory 22 and register file 20 can be utilized by system program code which is stored in instruction memory 23. Emulation unit 50 provides means for emulating the unprotected pipeline of microprocessor 1 and for rapidly uploading and downloading memories 22-23. Emulation unit 50 operates in a manner to prevent extraneous operations from occurring which could otherwise affect memories 22-23 or peripheral devices 60-61 during emulation.

Abstract: A method, apparatus, and article of manufacture and memory for providing a programming development environment that supports the development of Internet and Intranet applications. More specially, the present invention discloses an efficient, versatile dynamic debugger that allows platform-independent debugging of applications written in a wide variety of languages.

Abstract: A significant amount of software development is evolutionary, involving the modification of already existing programs. To a large extent, the modified programs produce the same results as the original program. This similarity between the original program and the development program is utilized by relative debugging. Relative debugging is a new concept that enables the user to compare the execution of two programs by specifying the expected correspondences between their states. A relative debugger concurrently executes the programs, verifies the correspondences, and reports any differences found. We describe our novel debugger called Guard, and its relative debugging capabilities. Guard is implemented by using our library of debugging routines, called Dynascope, which provides debugging primitives in heterogeneous networked environments. To demonstrate the capacity of Guard for debugging in heterogeneous environments, we describe an experiment in which the execution of two programs is compared across Internet. The programs are written in different programming languages and executing on different computing platforms.

Abstract: Designing and implementing a visual debugger for distributed programs is a significant challenge. Distributed applications are often large and frequently exhibit a high degree of complexity. Consequently, a debugger must address problems of complexity and scale in at least two ways. First, appropriate user interfaces should allow a user to manage the vast amount of information typically obtained from distributed executions. Second, the tool itself, in handling this information, should be implemented efficiently, providing a user with reasonable response times for interactive use. Our research efforts, concentrating on these problems, have led to the development of Poet, a tool for the collection and presentation of event-based traces of distributed executions. Poet makes as few assumptions as possible about characteristics that must be possessed by all target environments. Information describing each target environment is placed in configuration files, allowing a single set of Poet executables to be used for all target environments. Comparing Poet's performance to XPVM, the standard visualization tool for PVM executions, reveals that this target-system independence does not impose a performance penalty.