Abstract: An integrated software architecture for a highly parallel multiprocessor system having multiple tightly-coupled processors that share a common memory efficiently controls the interface with and execution of programs on such a multiprocessor system. The software architecture combines a symmetrically integrated multithreaded operating system and an integrated parallel user environment. The operating system distributively implements an anarchy-based scheduling model for the scheduling of processes and resources by allowing each processor to access a single image of the operating system stored in the common memory that operates on a common set of operating system shared resources. The user environment provides a common visual representation for a plurality of program development tools that provide compilation, execution and debugging capabilities for multithreaded user programs and assumes parallelism as the standard mode of operation.

Abstract: A system (Figure 10) for inserting code markers for observing indications (external to the microprocessor upon which the software operates) of the occurrence of an event in the execution of the software. Additional instructions or markers are added to the software to be debugged to produce simple, encoded, memory references to otherwise unused memory or I/O locations that will always be visible to a logic analyzer as bus cycles. Although the code markers cause a minimal intrusion in the underlying software, they make tracing events by a conventional logic analyzer much simpler and allow for performance evaluations in manners not heretofore possible. In particular, the inserted code markers provide a method of dynamically extracting information from a running host or real-time "black box" embedded system (902) under test using simple low intrusion print statements, encoded I/O writes on procedure entries and exits, and/or an interface to service calls and the like which writes out the passed parameters. Generally, the code markers are inserted at compile time or interactively during the debug session to make visible critical points in the code execution, such as function calls, task creation, semaphore operations and other resource usage so as to speed isolation of problems at test points during debugging. Performance analysis and event analysis use the code markers of the invention to cut through the ambiguities of microprocessor prefetch and cache operations. Because of these features, the invention is particularly advantageous for use by software design teams developing complex embedded host or real-time operating systems using multi-task operating systems and/or object oriented systems.

Abstract: Execution replay is a crucial part of debugging. Because explicitly parallel shared-memory programs can be nondeterministic, a tool is required that traces executions so they can be replayed for debugging. We present an adaptive tracing strategy that is optimal and records the minimal number of shared-memory references required to exactly replay executions. Our algorithm makes runtime tracing decisions by detecting and tracing a certain type of race condition on-the-fly . Unlike past schemes, we make no assumptions about the execution’ s correctness (it need not be race free). Experiments show that only 0.01−2% of the shared-memory references are usually traced, a 2−4 order of magnitude reduction over past techniques which trace every access.

Abstract: interpretation is a formal method that enables the static determination (i.e. at compile-time) of the dynamic properties (i.e. at run-time) of programs. We present an abstract interpretation-based method, called abstract debugging, which enables the static and formal debugging of programs, prior to their execution, by finding the origin of potential bugs as well as necessary conditions for these bugs not to occur at run-time. We show how invariant assertions and intermittent assertions, such as termination, can be used to formally debug programs. Finally, we show how abstract debugging can be effectively and efficiently applied to higher-order imperative programs with exceptions and jumps to non-local labels, and present the Syntox system that enables the abstract debugging of the Pascal language by the determination of the range of the scalar variables of programs.

Abstract: Traditionally, network software has been structured in a monolithic fashion with all protocol stacks executing either within the kernel or in a single trusted user-level server. This organization is motivated by performance and security concerns. However, considerations of code maintenance, ease of debugging, customization, and the simultaneous existence of multiple protocols argue for separating the implementations into more manageable user-level libraries of protocols. The present paper describes the design and implementation of transport protocols as user-level libraries. The authors begin by motivating the need for protocol implementations as user-level libraries and placing their approach in the context of previous work. They then describe their alternative to monolithic protocol organization, which has been implemented on Mach workstations connected not only to traditional Ethernet, but also to a more modern network, the DEC SRC AN1. Based on the authors' experience, they discuss the implications for host-network interface design and for overall system structure to support efficient user-level implementations of network protocols. >

Abstract: An architectural framework that allows software applications and operating system code written for a given instruction set to migrate to different, higher performance architectures is described. The framework provides a hardware mechanism that enhances application performance while keeping the same program behavior from a user perspective. The framework is designed to accommodate program exceptions, self-modifying code, tracing, and debugging. Examples are given for IBM System/390 operating-system code and AIX utilities, showing the performance potential of the scheme using a very long instruction word (VLIW) machine as the high-performance target architecture. >

Abstract: The memory consistency model (or memory model) of a shared-memory multiprocessor system influences the performance and the programmability of the system. The most intuitive model for programmers, sequential consistency, restricts many performance-enhancing optimizations. For higher performance, several alternative models have been proposed. The hardware-centric nature of these models, however, makes them difficult to program and inhibits portability. We use a 3P criteria of programmability, portability, and performance to assess memory models, and find current models lacking. This thesis establishes a unifying framework for designing memory models that can adequately satisfy the 3P criteria. The first contribution of this thesis is a programmer-centric methodology, called sequential consistency normal form (SCNF), for specifying memory models. SCNF is based on the observation that a system can employ performance-enhancing optimizations without violating sequential consistency if the system has some information about the program. An SCNF model is a contract between the system and the programmer, where the system guarantees high performance and sequential consistency only if the programmer provides certain information about the program. Insufficient information gives lower performance, but incorrect information violates sequential consistency. SCNF satisfies the 3P criteria of programmability (by providing sequential consistency), portability (by providing a common interface of sequential consistency across all models), and performance (by only requiring sequential consistency for programs with correct information). The second contribution demonstrates the effectiveness of SCNF by applying it to optimizations of previous hardware-centric models, resulting in four SCNF models. Although based on intuition similar to the hardware-centric models, these SCNF models are easier to program, enhance portability, and allow more implementations (with potentially higher performance) than the corresponding hardware-centric models. The third contribution culminates the above work by exposing a large part of the design space of SCNF models. SCNF models are difficult to design because the relationship between system optimizations and programmer information is complex. We simplify this relationship and use it to characterize and explore the design space. The final contribution concerns debugging programs on SCNF models. While debugging, the programmer may unknowingly provide incorrect information, violating sequential consistency. We apply debugging techniques for sequential consistency to two of the SCNF models to alleviate this problem.

Abstract: Non-concurrency analysis is a set of techniques for statically identifying pairs (or sets) of statements in a concurrent program which can never happen together. This information aids programmers in debugging and manually optimizing programs, improves the precision of data flow analysis, enables optimized translation of rendezvous, facilitates dead code elimination and other automatic optimizations, and allows anomaly detection in explicitly parallel programs. We present a framework for non-concurrency analysis, capable of incorporating previous analysis algorithms [CS88, DS92] and improving upon them. We show general theoretical results which are useful in estimating non-concurrency, and examples of non-concurrency analysis frameworks for two synchronization primitives: the Ada rendezvous and binary semaphores. Both of these frameworks have a low-order polynomial bound on worst-case solution time. We provide experimental evidence that static non-concurrency analysis of Ada programs can be accomplished in a reasonable time, and is generally quite accurate. Our framework, and the set of refinement components we develop, also exhibits dramatic accuracy improvements over [DS91], when the latter is used as a stand-alone algorithm, as demonstrated by our experiments.

Abstract: Presented here are efficient algorithms for checkpointing on MIMD architectures. These algorithms have been implemented on two representative machines: a shared-memory multiprocessor, and a message-passing multicomputer. The algorithms and implementations are evaluated according to three speed metrics: checkpoint time, overhead, and latency. Checkpointing is important as a general means of software fault-tolerance. It is also the backbone of certain program control utilities, such as job-swapping, process migration, and playback debugging. We employ several techniques to minimize the invasiveness of the checkpointer on the target program. Such techniques are main memory checkpointing, copy-on-write, buffering, compression, and the elimination of bottlenecks and extra control messages. The major result of this dissertation is that we can implement efficient checkpointing on MIMD architectures, thereby enhancing the usability of such machines.

Abstract: The authors' experiences with visualization and debugging of parallel virtual machine (PVM) applications and two of the tools they have devised to facilitate these tasks are described. One of the tools is a graphical monitoring package called Xab that can visually display PVM activities inside an application running across a network. The other is a graphical programming environment called Hence, which helps the user write, compile, execute, and trace heterogeneous distributed programs. The authors discuss their early work, the present research, and the future directions of these experimental projects. >

Abstract: There is a lack of methodologies and support tools for debugging and testing expert systems. This dissertation describes methodologies for testing and debugging expert systems. A tool which supports these methodologies is described. In addition to the methodologies of testing and debugging expert systems, this dissertation presents a measure of expert system complexity, a new proposal for a variety of data structured testing, and some recommended restrictions on the design of expert systems. A measure of expert system complexity was designed for use in the methodologies. This measure is based on the pattern of data usage among the rules. The complexity measure guides the user in selecting the test case coverage criterion. Data structured testing is discussed as another test case coverage criterion. It is not included in the testing methodology. The methodology for testing expert systems contains steps before system execution, a list of the most common mistakes that knowledge engineers or expert system developers commit while developing expert systems and how to avoid or reduce them, coverage measures, test case generation, and test case application. The methodology for debugging expert systems contains hypotheses generation, hypotheses testing, hypotheses revision, problem correcting, and regression testing. The tool called Simpler Level Five (SL5) was designed and implemented to support the methodologies. The features of the tool are detection of infinite loops, detection of faulty paths in expert systems, identification of redundant conditions of a rule, detection of tautology rules, identification of contradictory rules, a capability to ask which rule last set the value of a particular variable, a capability to set initial breakpoints, automatic development of comprehensive test cases, single stepping mode, selective enabling and disabling of individual rules, a capability to make notes in a file without leaving the debugger, a capability to ask the system to detect and announce particular conditions, a capability to ask for the last six executed rules, a capability to ask for the current value of an attribute and change it, a capability to search for uses of an attribute, and a capability for the graphical display of execution paths through the rule set.

Abstract: A computer program is executed in a forward direction to create a current state of registers and memory for the program. During the forward execution of the program, the pre-existing values of registers and memory changed by each instruction are recorded in a main log. During interactive debugging, reverse execution is simulated by displaying the contents of specified registers or memory locations. For each specified register or memory location, the main log is searched in a forward direction beginning at a specified time in the past and continuing until a value is found, or until the end of the main log is reached and a value is taken from the current state for the computer program. After simulated execution in reverse, the user may specify a changed value for a specified register or memory location, and then forward instruction interpretation is begun using the changed value, without changing the current state. New values of registers and memory locations generated by forward interpretation are recorded in an alternative log. Values of registers and memory accessed by forward-interpreted instructions are fetched by first searching the alternative log in a reverse direction, and when a value is not found in the alternative log, the main log is searched in a forward direction as described above. Moreover, at any time during forward interpretation, the user may specify a changed value, the change is logged in an alternative log, and forward interpretation continues.

Abstract: An object-oriented technology is provided which is capable of operating interpretively to allow prompt and easy prototyping and debugging using a compiled class library, and which is also capable of operating after compilation, thereby providing excellent performance. A software facility allows direct access to class attributes and direct invocation of class methods defined in pre-compiled classes in a class library in an interpretive mode. When this facility is used with or embedded within an application development environment, it allows an application builder to interactively build prototypes as well as production quality applications rapidly. When the facility is integrated with an object-oriented database, it allows interactive query and data manipulation using pre-complied classes.

Abstract: Achieving high performance for parallel or distributed programs often requires substantial amounts of information about the programs themselves, about the systems on which they are executing, and about specific program runs. The monitoring system that collects, analyzes, and makes application-dependent monitoring information available to the programmer and to the executing program is presented. The system may be used for off-line program analysis, for on-line debugging, and for making on-line, dynamic changes to parallel or distributed programs to enhance their performance. The authors use a high-level, uniform data model for the representation of program information and monitoring data. They show how this model may be used for the specification of program views and attributes for monitoring, and demonstrate how such specifications can be translated into efficient, program-specific monitoring code that uses alternative mechanisms for the distributed analysis and collection to be performed for the specified views. The model's utility has been demonstrated on a wide variety of parallel machines. >

Abstract: A non-intrusive method and system for recovering the state of a computer system including a memory having first and second matched levels. The first level is connected to a target processor and the second level is connected to a checkpoint processor which is also connected to the target processor. In an example of the invention, a two phase, non-intrusive method and system for debugging parallel computer programs is provided. The program has checkpoint instructions therein. In the first phase the execution of the program is monitored non-intrusively from a bus connecting the target processor to the first level of memory. A sequence of relevant program instructions is stored in an event table. Upon encountering a checkpoint instruction, the target processor cues the checkpoint processor to initiate a non-intrusive checkpointing strategy utilizing the two-level memory with an E-bit scheme. In the second phase the information collected during the first phase is utilized to replay an identical execution of the program, in a simulated environment. A user, on encountering an error, can back up to a previous checkpoint and replay the program from that state of the computer system.

Abstract: Algorithm animation presents a dynamic visualization of an algorithm or program. This work seeks to bridge the two domains of data structure display and algorithm animation. The application-specific nature of algorithm animation views could be a valuable debugging aid for software developers. A system called Lens was developed that allows programmers to rapidly develop animations of their programs. Lens supports application-specific semantic program views as seen in many algorithm animation systems, but does not require graphics programming. Lens is integrated with a system debugger to support iterative testing and refinement. The authors describe the conceptual model on which Lens is based, illustrate how program animations are built with Lens, and outline some of the implementation challenges the system presents. >

Abstract: This chapter contains sections titled: Introduction, Language, Revising Contradictory Extended Logic Programs, Application to Declarative Debugging, Application to Diagnosis, Acknowledgements, References

Abstract: This tutorial describes computer languages and other software packages that support discrete-event simulation.

Abstract: A system management mode (SMM), an external dedicated system management memory (SMRAM), a system management interrupt (SMI), a SMI service handler with an integrated debugger, a Resume instruction (RSM), and at least one way for triggering a SMI as a result of a debugging request is provided to a computer system. Debugging is performed under SMM with the integrated debugger which is stored with the SMI handler in the SMRAM and given control after the SMI handler has gotten control and determined in its initial processings that the SMI handler has gotten control as a result of a SMI triggered by a debugging request. The SMI handler gets control after the computer system is put into SMM in response to the SMI. Upon exiting the integrated debugger, the SMI handler executes the RSM instruction to continue execution with the interrupted program. As a result, debugging may be performed with the actual hardware in its normal operating speed, and yet debugging functions and usability matching or exceeding that of a software emulator may be provided. Additionally, debugging may be performed in a manner that is transparent to the operating system and the application programs.

Abstract: Emerging database application domains demand not only high functionality, but also high performance. To satisfy these two requirements, the Volcano query execution engine combines the efficient use of parallelism on a wide variety of computer architectures with an extensible set of query processing operators that can be nested into arbitrarily complex query evaluation plans. Volcano's novel exchange operator permits designing, developing, debugging, and tuning data manipulation operators in single-process environments but executing them in various forms of parallelism. The exchange operator shields the data manipulation operators from all parallelism issues. The design and implementation of the generalized exchange operator are examined. The authors justify their decision to support hierarchical architectures and argue that the exchange operator offers a significant advantage for development and maintenance of database query processing software. They discuss the integration of bit vector filtering into the exchange operator paradigm with only minor modifications. >

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Abstract: Formal design verification should be used to reveal bugs early in the design cycle. A tool exhibiting counter-examples (a debugger) is therefore essential. We describe debugging techniques for two important approaches to formal design verification: model checking using Computation Tree Logic ([Cla86]) and language containment using L-automata ([Kur90]).

Abstract: A debugger is used in an environment of optimized compiling to track both user-defined and synthesized variables so that the values of these variables at selected programmer counter addresses can be either determined or set. The tracking is primarily accomplished by the generation of various interrelated tables including a Type Scope Table, a Name Space Table, an Expression Table, a Location Range Table and a Variable Table. These tables define the existence of variables at defined program counter ranges and provide the algebraic definitions for the synthesized variables. A programmer can efficiently debug a program produced with optimized compiling through the operations of determining variable values and setting variable values.

Abstract: Xab is a run time monitoring tool for parallel virtual machine (PVM) programs. Xab gives the user direct feedback as to what PVM functions his or her program is performing. In its most simple form, this feedback is displayed in a window. The approach of real time monitoring is particularly apropos in a heterogeneous multiprogramming environment. Differences in computation and communication speeds here are due both to heterogeneity and external CPU and network loads. Monitoring can help give the user insight into how a program is behaving in such an environment. Xab is a continuing research project. The author discusses several related research projects, the current version of Xab, and the future development of the Xab tool. >