TL;DR: In this paper, a system and method for performing data transfers within a computer system is presented, which includes a controller configured to dynamically adjust the interleave of the communications required to perform a series of data transfer operations to maximize utilization of the channel over which the communications are to be performed.
Abstract: A system and method for performing data transfers within a computer system is provided. The system includes a controller configured to dynamically adjust the interleave of the communications required to perform a series of data transfer operations to maximize utilization of the channel over which the communications are to be performed. The controller is able to vary the time interval between the transmission of control information that requests a data transfer and the performance of the data transfer by signaling the beginning of the data transfer with a strobe signal sent separate from the control information. The controller is able to defer the determination of how much data will be transferred in the operation by initiating the termination of a data transfer with a termination signal. The method provides a technique for distinguishing between identical control signals that are carried on the same line. The system includes a memory device with control circuitry that allows no more than one memory bank powered by any given power supply line to perform sense or precharge operations.
TL;DR: In this paper, an integrated circuit memory device is designed to perform high speed data write cycles, where the address is incremented internal to the device with additional address strobe transitions.
Abstract: An integrated circuit memory device is designed to perform high speed data write cycles. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. A transition of the Read/Write control line during a burst access is used to terminate the burst access and initialize the device for another burst access. Write cycle times are maximized to allow for increases in burst mode operating frequencies. Local logic gates near array sense amplifiers are used to control write data drivers to provide for maximum write times without crossing current during input/output line equilibration periods. By gating global write enable signals with global equilibrate signals locally at data sense amp locations, local write cycle control signals are provided which are valid for essentially the entire cycle time minus an I/O line equilibration period in burst access memory devices. For nonburst mode memory devices such as EDO and Fast Page Mode, the write function may begin immediately following the end of the equilibration cycle to provide a maximum write time without interfering with the address setup time of the next access cycle.
TL;DR: In this article, phase information acquired from a timing reference signal such as a strobe signal was used to align a data-sampling signal for sampling a data signal that was sent along with the timing reference signals.
Abstract: An apparatus that reduces sampling errors for data communicated between devices uses phase information acquired from a timing reference signal such as a strobe signal to align a data-sampling signal for sampling a data signal that was sent along with the timing reference signal. The data-sampling signal may be provided by adjustably delaying a clock signal according to the phase information acquired from the strobe signal. The data-sampling signal may also have an improved waveform compared to the timing reference signal, including a fifty percent duty cycle and sharp transitions. The phase information acquired from the timing reference signal may also be used for other purposes, such as aligning received data with a local clock domain, or transmitting data so that it arrives at a remote device in synchronism with a reference clock signal at the remote device.
TL;DR: In this paper, a signaling system for a first integrated circuit (IC) to receive a data signal and a strobe signal is presented. But the system is limited to a single IC and it requires the first IC to sample the data signal at times indicated by the strobe signals to generate phase error information.
Abstract: A signaling system is disclosed. The signaling system includes a first integrated circuit (IC) chip to receive a data signal and a strobe signal. The first IC includes circuitry to sample the data signal at times indicated by the strobe signal to generate phase error information and circuitry to output the phase error information from the first IC device. The system further includes a signaling link and a second IC chip coupled to the first IC chip via the signaling link to output the data signal and the strobe signal to the first IC chip. The second IC chip includes delay circuitry to generate the strobe signal by delaying an aperiodic timing signal for a first time interval and timing control circuitry to receive the phase error information from the first IC chip and adjust the first time interval in accordance with the phase error information.
TL;DR: In this article, a touch-sensored display device with a counter substrate and a strobe signal generation circuit is presented. But the counter substrate is disposed on a viewer side of an active matrix substrate via a display medium layer and the counter electrode has a counter electrode which opposes pixel electrodes.
Abstract: A touch-sensored display device 20 according to the present invention includes: a counter substrate 6 disposed on a viewer side of an active matrix substrate 8 via a display medium layer 4, the counter substrate 6 having a counter electrode 5 which opposes pixel electrodes; a display panel driving circuit 14 for supplying to the counter electrode 5 a common voltage which undergoes periodic inversion in polarity; a transparent conductive film 7 for position detection placed so as to oppose the counter electrode 5 via the counter substrate 6; a strobe signal generation circuit 32 for generating a strobe signal which is in synchronization with a polarity inversion period of the common voltage, and a noise-cut current signal generation circuit 30 for generating a noise-cut current signal which is obtained by eliminating based on the strobe signal a predetermined portion from a current flowing from a terminal connected to the transparent conductive film 7 for position detection