About: Current divider is a research topic. Over the lifetime, 3509 publications have been published within this topic receiving 33961 citations. The topic is also known as: current divider rule.
TL;DR: In this article, a modular and power-scalable architecture for low-power programmable frequency dividers is presented, which consists of a 17-bit UHF divider, an 18-bit L-band divider and a 12-bit reference divider.
Abstract: A truly modular and power-scalable architecture for low-power programmable frequency dividers is presented. The architecture was used in the realization of a family of low-power fully programmable divider circuits, which consists of a 17-bit UHF divider, an 18-bit L-band divider, and a 12-bit reference divider. Key circuits of the architecture are 2/3 divider cells, which share the same logic and the same circuit implementation. The current consumption of each cell can be determined with a simple power optimization procedure. The implementation of the 2/3 divider cells is presented, the power optimization procedure is described, and the input amplifiers are briefly discussed. The circuits were processed in a standard 0.35 /spl mu/m bulk CMOS technology, and work with a nominal supply voltage of 2.2 V. The power efficiency of the UHF divider is 0.77 GHz/mW, and of the L-band divider, 0.57 GHz/mW. The measured input sensitivity is >10 mV rms for the UHF divider, and >20 mV rms for the L-band divider.
TL;DR: The examined class of circuits includes voltage multipliers, current multiplier circuits, linear V-I convertors, linear I-V convertor circuits, current squaring circuits, and current divider circuits.
Abstract: The examined class of circuits includes voltage multipliers, current multipliers, linear V-I convertors, linear I-V convertors, current squaring circuits, and current divider circuits. Typical for these circuits is an independent control of the sum as well as the difference between two gate-source voltages. As direct use is made of the basic device characteristics, only a small number of transistors is required in the presented circuits.
TL;DR: In this article, a phase-locked loop (PLL) was used for fractional-N frequency synthesis using oversampling A/D conversion technology, allowing the spectrum of error energy to be shaped so that fractional synthesis error energy is pushed away from the carrier.
Abstract: Fractional-N frequency synthesis using a phase locked loop (PLL) is considered. Advances in oversampling A/D conversion technology are incorporated into fractional-N synthesis, allowing the spectrum of error energy to be shaped so that fractional synthesis error energy is pushed away from the carrier. Based on this new technology, a CMOS integrated fractional-N divider was successfully developed. A complete fractional-N PLL was constructed utilizing only a CMOS divider, a dual modulus prescaler, a simple loop filter, and a voltage controlled oscillator (VCO). The resulting PLL exhibits no fractional spurs. >
TL;DR: In this paper, an ultra wideband (UWB) power divider on microstrip line is proposed, analyzed and designed, which is formed by installing a pair of stepped-impedance open-circuited stubs and parallel-coupled lines to two symmetrical output ports.
Abstract: An ultra-wideband (UWB) power divider on microstrip line is proposed, analyzed and designed. This divider is formed by installing a pair of stepped-impedance open-circuited stubs and parallel-coupled lines to two symmetrical output ports. In addition, a single resistor is properly placed between two output ports. After simple transmission line theory analysis, it is demonstrated that 3 dB power splitting from one input to two output ports, good impedance matching at all the three ports and excellent isolation between two output ports are achieved over the specified 3.1-10.6 GHz UWB range. Finally, a prototype divider is fabricated and measured to provide an experimental verification on the predicted attractive features.
TL;DR: In this paper, the design of a compact out-of-phase uniplanar power divider operating over an ultra wide frequency band is presented, where a T-junction formed by a slotline and a microstrip line accompanied by wideband microstrip to slotline transitions is employed.
Abstract: The design of a compact out-of-phase uniplanar power divider operating over an ultra wide frequency band is presented. To achieve an out-of-phase signal division over a large frequency range, a T-junction formed by a slotline and a microstrip line accompanied by wideband microstrip to slotline transitions is employed. The simulated and experimental results of the developed divider show a low insertion loss and good return loss performance of the three ports across the band 3.1-10.6 GHz