Topic
CRC-based framing
About: CRC-based framing is a research topic. Over the lifetime, 39 publications have been published within this topic receiving 382 citations.
Papers
29 May 2001
TL;DR: A mechanism to defer CRC verification without compromising reliability is presented, which opens the possibility of incremental updates of the CRC and applies to a much wider set of network protocols.
Abstract: In response to the increasing network speeds, many operations in IP routers and similar devices are being made more efficient. With the advances in other areas of packet processing, the verification and regeneration of cyclic redundancy check (CRC) codes of the data link layer is likely to become a bottleneck in the near future. In this paper, we present a mechanism to defer CRC verification without compromising reliability. This opens the possibility of incremental updates of the CRC. We introduce a new high-speed technique and present efficient implementations, speeding up CRC processing by a factor of 15. Although the paper and analysis focuses on IP over ATM, the scheme applies to a much wider set of network protocols.
64 citations
Patent•
23 Nov 2005TL;DR: In this article, a cyclic redundancy check (CRC) checker is provided that includes a unique pattern detector, a CRC generator, an initializer and a CRC verifier.
Abstract: The present invention provides systems and methods for implementing cyclic redundancy checks to improve link initialization processing and to exchange system error information. In one aspect, a cyclic redundancy check (CRC) checker is provided that includes a unique pattern detector, a CRC generator, a CRC initializer and a CRC verifier. The CRC checker prepopulates the CRC generator for a unique pattern. Upon receipt of the unique pattern within a data stream received over a digital transmission link, the CRC checker proceeds to check CRCs without the need to queue and store data. In another aspect, a CRC generator system is provided that intentionally corrupts CRC values to transmit system error information. The CRC generator system includes a CRC generator, a CRC corrupter, an error detector and an error value generator. In one example, the digital transmission link is an MDDI link.
43 citations
22 Apr 2015
TL;DR: A high performance table-based architecture implementation for CRC (cyclic redundancy check) algorithms is proposed, designed based on a highly parallel CRC algorithm that can accelerate different CRC algorithms with high parallelism and flexibility.
Abstract: A high performance table-based architecture implementation for CRC (cyclic redundancy check) algorithms is proposed. The architecture is designed based on a highly parallel CRC algorithm. The algorithm first divides a given message with any length into bytes. Then it performs CRC computation using lookup tables among the divided bytes in parallel. At last, the results are XORed to obtain the CRC value of the given message. The algorithm is table-based and can accelerate different CRC algorithms. Based on the algorithm, the architecture is designed to accelerate CRC algorithms with high parallelism and flexibility. The architecture is configurable and can support CRC algorithms such as CRC32, CRC24, CRC-CCITT, CRC16, CRC8. CRC value of 128-bit input data can be generated in one cycle. Our method also allows calculation over data that is less than 128-bit wide without increasing hardware cost. With 128-bit input each clock cycle, the throughput of the proposed architecture reaches up to 100 Gbps by utilizing 16 KB SRAM (Static Random Access Memory) with about 12% area reduction compared with previous work.
30 citations
Patent•
19 Nov 1984
TL;DR: Frame bit synchronizer for a framing pattern sequence consisting of M bits distributed in a serial bit stream as single bits at intervals of a fixed number N, of bits, as measured from the start of one framing bit to start of the next as discussed by the authors.
Abstract: Frame bit synchronizer for a framing pattern sequence consisting of M Bits distributed in a serial bit stream as single bits at intervals of a fixed number N, of bits, as measured from the start of one framing bit to the start of the next The system initially operates in a framing mode, searching for frame, until the framing pattern sequence has been determined, upon which event the operation shifts to an in-frame monitoring mode for detecting errors in the framing pattern sequence in the serial bit stream as received
20 citations
TL;DR: It is shown that 32 bit CRC used in SEAL provides robust detection of cell misordering, for any frame size up to 4 Gb, the probability of undetected misordering is 2/sup -32/.
Abstract: The performance of a 32 bit cyclic redundancy check (CRC) for detecting cell misordering in an asynchronous transfer mode adaptation layer, called simple and efficient adaptation layer (SEAL), is discussed. It is shown that 32 bit CRC used in SEAL provides robust detection of cell misordering. For any frame size up to 4 Gb, the probability of undetected misordering is 2/sup -32/. >
19 citations
Related Topics (5)
Performance Metrics
| Year | Papers |
|---|---|
| 2015 | 4 |
| 2014 | 4 |
| 2013 | 2 |
| 2012 | 2 |
| 2009 | 2 |
| 2007 | 1 |