Copper interconnect

Abstract: Damascene Cu electroplating for on-chip metallization, which we conceived and developed in the early 1990s, has been central to IBM's Cu chip interconnection technology. We review here the challenges of filling trenches and vias with Cu without creating a void or seam, and the discovery that electrodeposition can be engineered to give filling performance significantly better than that achievable with conformal step coverage. This attribute of superconformal deposition, which we call superfilling, and its relation to plating additives are discussed, and we present a numerical model that represents the shape-change behavior of this system.

Abstract: A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate dielectric, dual band edge workfunction metal gates and third generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. The technology also features trench contact based local routing, 9 layers of copper interconnect with low-k ILD, low cost 193 nm dry patterning, and 100% Pb-free packaging. Process yield, performance and reliability are demonstrated on 153 Mb SRAM arrays with SRAM cell size of 0.346 mum2, and on multiple microprocessors.

Abstract: Damascene copper electroplating for on-chip interconnections, a process that we conceived and developed in the early 1990s, makes it possible to fill submicron trenches and vias with copper without creating a void or a seam and has thus proven superior to other technologies of copper deposition. We discuss here the relationship of additives in the plating bath to superfilling, the phenomenon that results in superconformal coverage, and we present a numerical model which accounts for the experimentally observed profile evolution of the plated metal.

Abstract: (NOTE: Each chapter concludes with Summary, References, and Problems) Preface 1 An Overview of Microelectronic Fabrication A Historical Perspective An Overview of Monolithic Fabrication Processes and Structures Metal-Oxide-Semiconductor (MOS) Processes Basic Bipolar Processing Safety 2 Lithography The Photolithographic Process Etching Techniques Photomask Fabrication Exposure Systems Exposure Sources Optical and Electron Microscopy Further Reading 3 Thermal Oxidation of Silicon The Oxidation Process Modeling Oxidation Factors Influencing Oxidation Rate Dopant Redistribution During Oxidation Masking Properties of Silicon Dioxide Technology of Oxidation Oxide Quality Selective Oxidation and Shallow Trench Formation Oxide Thickness Characterization Process Simulation 4 Diffusion The Diffusion Process Mathematical Model for Diffusion The Diffusion Coefficient Successive Diffusions Solid-Solubility Limits Junction Formation and Characterization Sheet Resistance Generation-Depth and Impurity Profile Measurement Diffusion Simulation Diffusion Systems Gettering 5 Ion Implantation Implantation Technology Mathematical Model for Ion Implantation Selective Implantation Junction Depth and Sheet Resistance Channeling, Lattice Damage, and Annealing Shallow Implantation Source Listing 6 Film Deposition Evaporation Sputtering Chemical Vapor Deposition Epitaxy Further Reading 7 Interconnections and Contacts Interconnections in Integrated Circuits Metal Interconnections and Contact Technology Diffused Interconnections Polysilicon Interconnections and Buried Contacts Silicides and Multilayer-Contact Technology The Liftoff Process Multilevel Metallization Copper Interconnects and Damascene Processes Further Reading 8 Packaging and Yield Testing Wafer Thinning and Die Separation Die Attachment Wire Bonding Packages Flip-Chip and Tape-Automated-Bonding Processes Yield Further Reading 9 MOS Process Integration Basic MOS Device Considerations MOS Transistor Layout and Design Rules Complementary MOS (CMOS) Technology Silicon on Insulator 10 Bipolar Process Integration The Junction-Isolated Structure Current Gain Transit Time Basewidth Breakdown Voltages Other Elements in SBC Technology Layout Considerations Advanced Bipolar Structures Other Bipolar Isolation Techniques BICMOS 11 Processes for Microelectromechanical Systems-MEMS Mechanical Properties of Silicon Bulk Micromachining Silicon Etchants Surface Micromachining High-Aspect-Ratio Micromachining: The LIGA Molding Process Silicon Wafer Bonding IC Process Compatibility Answers to Selected Problems Index