Control store

Abstract: A microprocessor integrator circuit includes split nanocode memories which enables simultaneous execution of an arithmetic operation and an operand fetch for maximizing through-put. The circuit also includes a shared sequencing arithmetic logic unit which handles all microcode sequencing plus memory address sequencing. The circuit also provides nanocode sequencing which enables storage of constants and data in a microcode space which can include an off-chip writable control store. In addition, two level microcode is utilized to enable long routines to be vertically encoded without the overhead of a large number of read only memory outputs.

Abstract: An apparatus (104, 106) is described that facilitates network security and network traffic monitoring through processing of network traffic in accordance with provisioned rules and policies. The apparatus includes a set of microcode controlled state machines, each of which applies one or more rules to input network traffic. A distribution circuit routes individual network traffic segments derived from input network traffic to the set of microcode controlled state machines, so that each individual segment is processed in accordance wit microcode stored in an associated control store. Each microcode controlled state machine includes a computation kernel operating in accordance with the microcode. An aggregation circuit routes the resulting processed individual network traffic segments in accordance with an output routing policy to produce output network traffic corresponding to the original input network traffic. Advantageously, the apparatus provides an architectural framework well suited to a low cost, high speed, robust implementation of flexible, advanced network security features and network traffic analysis.

Abstract: The application of microprogramming in present day computers is rapidly increasing and microprogramming will undoubtedly play a major role in the next generation of computer systems. Microprogram optimization is one way to increase efficiency and can be crucial in some applications. Optimization, in this context refers to a reduction/minimization of control store and/or execution time of microprograms. The numerous strategies are classified under four broad categories: word dimension reduction, bit dimension reduction, state reduction, and heuristic reduction. The various techniques are presented, analyzed, and compared. Unfortunately, the results of the survey are not too positive. The reason is that much of the work on optimization has been devoted to obtaining the absolute minimum solutions rather than "good engineering reductions." Whether the reduction is being performed with respect to the word dimension, the bit dimension or the number of states existing techniques to obtain the optimum solution use exhaustive enumeration. Thus, the effort involved is prohibitive and there are no guarantees that significant reductions can be obtained. It is thus doubtful that an optimum solution can be justified even when the microcode produced is frequently executed. Heuristic reduction techniques do not guarantee an optimum solution but can provide some reduction with little effort. For the majority of the techniques studied, much further work remains to be done before any practical applications can be foreseen. Some methods however constitute steps in the right directions. Directions for future research are briefly outlined in the conclusions.

Abstract: A peripheral device controller has an EEPROM which stores microinstructions to be placed in a random access memory control store. The EEPROM also stores peripheral configuration information. This information is obtained by polling the peripheral devices connected to the controller and storing the resulting information in the EEPROM. Upon powering up, the microinstructions stored in the EEPROM are transferred to the control store via execution of instructions held in a boot PROM. The controller, therefore, provides a fast control store while maintaining permanence of the microinstructions after power is extinguished. Means are also provided to update the control store and EEPROM. The EEPROM may upon CPU command be updated with new microinstructions held in main memory or obtained from peripheral devices.