Topic
Constraint graph (layout)
About: Constraint graph (layout) is a research topic. Over the lifetime, 72 publications have been published within this topic receiving 1036 citations.
Papers published on a yearly basis
Papers
TL;DR: This is the first piece of work that can handle symmetry constraint, common centroid constraint, and other general placement constraints, simultaneously, simultaneously.
Abstract: In today's system-on-chip designs, both digital and analog parts of a circuit will be implemented on the same chip. Parasitic mismatch induced by layout will affect circuit performance significantly for analog designs. Consideration of symmetry and common centroid constraints during placement can help to reduce these errors. Besides these two specific types of placement constraints, other constraints, such as alignment, abutment, preplace, and maximum separation, are also essential in circuit placement. In this paper, we will present a placement methodology that can handle all these constraints at the same time. To the best of our knowledge, this is the first piece of work that can handle symmetry constraint, common centroid constraint, and other general placement constraints, simultaneously. Experimental results do confirm the effectiveness and scalability of our approach in solving this mixed constraint-driven placement problem.
94 citations
4 Mar 1999
TL;DR: This paper presents graph based algorithms for estimating the maximum leakage power, which are pattern-independent and do not require simulation of the circuit, and compares with exhaustive/long simulations for MCNC/ISCAS-85 benchmark circuits to verify the accuracy of the method.
Abstract: Low supply voltage requires the device threshold to be reduced in order to maintain performance. As the device threshold voltage is reduced, it results in an exponential increase of leakage current in the subthreshold region. The leakage power is no longer negligible in such low voltage circuits. Estimates of maximum leakage power can be used in the design of the circuit to minimize the leakage power. The leakage power is dependent on the input vector. This input pattern dependence of the leakage power makes the problem of estimating the maximum leakage power a hard problem. In this paper, we present graph based algorithms for estimating the maximum leakage power. These algorithms are pattern-independent and do not require simulation of the circuit. Instead the circuit structure and the logic functionality of the components in the circuit are used to create a constraint graph. The problem of estimating the maximum leakage power is then transformed to an optimization problem on the constraint graph. Efficient algorithms on the graph are used to estimate the maximum leakage power dissipated by a circuit. We also present comparisons with exhaustive/long simulations for MCNC/ISCAS-85 benchmark circuits to verify the accuracy of the method.
69 citations
1 Jan 1985
TL;DR: A comparison of WEAVER's Routing of a Channel Unroutable by the Greedy Algorithm and the Techniques of Applied AI shows that the former is more efficient and the latter is less efficient.
Abstract: 1. Introduction.- 1.1. Motivation.- 1.2. Outline.- 2. Detailed Routing.- 2.1. Problem Statement.- 2.2. Important Factors in Routing.- 2.3. Previous Approaches.- 2.3.1. Lee Algorithm.- 2.3.2. Line Routing Algorithms.- 2.3.3. Efficient Algorithms for Channel Routing.- 2.3.4. A "Greedy" Channel Router.- 2.3.5. Hierarchical Wire Routing.- 2.4. Characteristics of Previous Approaches.- 3. WEAVER Approach.- 3.1. Congestion.- 3.2. Wire Length.- 3.3. Rectilinear Steiner Tree.- 3.3.1. Steiner Tree.- 3.3.2. Minimal Rectilinear Steiner Tree for a 2xn Grid.- 3.3.3. Minimal Rectilinear Steiner Tree for A mxn Grid.- 3.4. Merging.- 3.5. Vertical/Horizontal Constraint Graph.- 3.6. Intersection.- 3.7. Conflicting Effects.- 4. Knowledge-Based Expert Systems.- 4.1. Productions Systems.- 4.2. OPS5.- 4.2.1. Working Memory.- 4.2.2. Production Memory.- 4.2.3. Interpreter.- 4.3. Applicability of Knowledge-Based Expert Systems to VLSI Design.- 4.3.1. Detailed Routing of VLSI Chips is Amenable to the Techniques of Applied AI.- 4.3.2. Detailed Routing of VLSI Chips is Important, Difficult and a High-Value Problem.- 4.4. Advantages and Disadvantages of Knowledge-Based Expert Systems.- 5. WEAVER Implementation.- 5.1. Problem State Representation.- 5.2. WEAVER Architecture.- 5.3. Blackboard Organization.- 5.4. WEAVER Experts.- 5.4.1. Wire Length Expert.- 5.4.2. Merging Expert.- 5.4.3. Congestion Expert.- 5.4.4. Vertical/Horizontal Constraint Expert.- 5.4.5. Via Expert.- 5.4.6. Common Sense Expert.- 5.4.7. Pattern Router Expert.- 5.4.8. Constraint Propagation Expert.- 5.4.9. User Expert.- 5.4.10. Minimal Rectilinear Steiner Tree Expert.- 5.5. WEAVER Control Structure.- 5.5.1. Nature of WEAVER Expertise.- 5.5.2. Generality of WEAVER Knowledge.- 5.6. Program Organization.- 6. Experiments and Results.- 6.1. Input/Output.- 6.1.1. Input.- 6.1.2. Output.- 6.2. Step by Step Trace of Routing a Channel.- 6.3. Experiments.- 6.3.1. Comparison with Efficient Algorithms for Channel Routing.- 6.3.2. Comparison with the Greedy Algorithm When Both can Route the Channel.- 6.3.3. WEAVER's Routing of a Channel Unroutable by the Greedy Algorithm.- 6.3.4. WEAVER's Solution to Provably Unroutable Channel and Switch-Box by Traditional Algorithms.- 6.3.5. Comparison with Aker's and Lee Algorithms.- 6.3.6. Comparison with the Minimum-Impact Routing Algorithm.- 6.3.7. Burstein's Difficult Switch-Box.- 6.3.8. Terminal Intensive Example.- 6.3.9. Dense Switch-Box Example.- 6.3.10. Conclusion to the Experiments.- 6.4. WEAVER's Performance Under Conditions of Disabled Experts.- 6.4.1. Merging Expert Disabled.- 6.4.2. Congestion and Merging Experts Disabled.- 6.4.3. Via Expert Disabled.- 6.4.4. Vertical/Horizontal Constraint Expert Partially Disabled.- 6.4.5. Rectilinear Steiner Tree Expert Disabled.- 6.4.6. Summary of the Results of Disabling the Experts.- 6.5. Efficiency Issues.- 6.5.1. Possible Execution Time Improvement.- 6.5.2. Writing Efficient OPS5 Programs.- 7. Conclusions and Future Work.- References.
61 citations
18 Jun 2018
TL;DR: A system that automatically extracts 3D geometry of an indoor scene from a single 2D panorama and uses the recovered layout to guide shape estimation of the remaining objects using their normal information is described.
Abstract: We describe a system that automatically extracts 3D geometry of an indoor scene from a single 2D panorama. Our system recovers the spatial layout by finding the floor, walls, and ceiling; it also recovers shapes of typical indoor objects such as furniture. Using sampled perspective sub-views, we extract geometric cues (lines, vanishing points, orientation map, and surface normals) and semantic cues (saliency and object detection information). These cues are used for ground plane estimation and occlusion reasoning. The global spatial layout is inferred through a constraint graph on line segments and planar superpixels. The recovered layout is then used to guide shape estimation of the remaining objects using their normal information. Experiments on synthetic and real datasets show that our approach is state-of-the-art in both accuracy and efficiency. Our system can handle cluttered scenes with complex geometry that are challenging to existing techniques.
61 citations
10 Jun 2002
TL;DR: A floorplanning algorithm based on sequence pair representation based on computing the longest common subsequence of a pair of weighted sequences that translates to a floorplan in O(n log log n) time, which is significantly faster than the O( n3) method operating on constraint graph.
Abstract: In this paper, we present a floorplanning algorithm based on sequence pair representation. Our floorplanner has the following important features: (1) It is explicitly designed for fixed-frame floorplanning, which is different from traditional well-researched min-area floorplanning. Moreover, we also show that it can be adapted to minimize total area. (2) It addresses the problem of handling alignment constraint which arises in bus structure. (3) It deals with performance constraint such as bounded net delay, while many existing floorplanners just minimize total wire length. (4) More importantly, even with all these constraints the algorithm is very fast in that it evaluates the feasibility of a sequence pair and translates to a floorplan in O(n log log n) time typically where n is the number of blocks and the number of constrained blocks is O(n), which is significantly faster than the O(n/sup 3/) method operating on constraint graph. Our algorithm is based on computing the longest common subsequence of a pair of weighted sequences. Experimental results on MCNC benchmark for block placement show the promise of the method.
51 citations
Performance Metrics
| Year | Papers |
|---|---|
| 2021 | 1 |
| 2020 | 2 |
| 2018 | 1 |
| 2017 | 2 |
| 2015 | 1 |
| 2014 | 1 |