Complex multiplier

Abstract: Two concurrent error detection (CED) schemes are proposed for N-point fast Fourier transform (FFT) networks that consists of log/sub 2/N stages with N/2 two-point butterfly modules for each stage. The method assumes that failures are confined to a single complex multiplier or adder or to one input or output set of lines. Such a fault model covers a broad class of faults. It is shown that only a small overhead ratio, O(2/log/sub 2/N) of hardware, is required for the networks to obtain fault-secure results in the first scheme. A novel data retry technique is used to locate the faulty modules. Large roundoff errors can be detected and treated in the same manner as functional errors. The retry technique can also distinguish between the roundoff errors and functional errors that are caused by some physical failures. In the second scheme, a time-redundancy method is used to achieve both error detection and location. It is sown that only negligible hardware overhead is required. However, the throughput is reduced to half that of the original system, without both error detection and location, because of the nature of time-redundancy methods. >

Abstract: In a high-power transmitter, an input complex signal is multiplied in a complex multiplier by control signals. The output complex signal from the multiplier is converted to a high frequency signal and amplified by a power amplifier for transmission. The amplitude of the input complex signal is detected to access a memory where amplitude and phase correction values are stored. During a read mode of the memory, a set of amplitude and phase correction values is specified by the detected amplitude and supplied to the complex amplifier as the control signals. During a write mode of the memory, a set of amplitude and phase correction values is specified by a delayed version of the detected amplitude and rewritten with a set of new amplitude and phase correction values. The amplified high frequency signal is down-converted to a low frequency complex signal. The nonlinearity of the power amplifier is determined from a delayed version of the input complex signal and the down-converted complex signal and the new amplitude and phase correction values are produced from the detected nonlineariry and delayed versions of the amplitude and phase correction values which were supplied to the complex multiplier. At intervals, the memory is switched from the read mode to the write mode for updating its contents.

Abstract: Vedic Mathematics is the ancient methodology of Indian mathematics which has a unique technique of calculations based on 16 Sutras (Formulae). A high speed complex multiplier design (ASIC) using Vedic Mathematics is presented in this paper. The idea for designing the multiplier and adder/sub-tractor unit is adopted from ancient Indian mathematics “Vedas”. On account of those formulas, the partial products and sums are generated in one step which reduces the carry propagation from LSB to MSB. The implementation of the Vedic mathematics and their application to the complex multiplier ensure substantial reduction of propagation delay in comparison with DA based architecture and parallel adder based implementation which are most commonly used architectures. The functionality of these circuits was checked and performance parameters like propagation delay and dynamic power consumption were calculated by spice spectre using standard 90nm CMOS technology. The propagation delay of the resulting (16, 16)×(16, 16) complex multiplier is only 4ns and consume 6.5 mW power. We achieved almost 25% improvement in speed from earlier reported complex multipliers, e.g. parallel adder and DA based architectures.

Abstract: This paper proposes a new modified radix-2 4 FFT algorithm and an efficient pipeline FFT architecture based on this algorithm for OFDM systems. This pipeline FFT architecture has the same number of multipliers as that of the radix-2 2 algorithm. However, the multiplication complexity could be reduced by more than 30% by replacing one half of the programmable multipliers by the newly proposed CSD constant multipliers. From the synthesis simulations of a standard 0.35μm CMOS SAMSUNG process, a proposed CSD constant complex multiplier achieved more than 60% area efficiency when compared to the conventional programmable complex multiplier. This promoted efficiency could be used to the design of a long length FFT processor in wireless OFDM applications, which needs more power and area efficiency.