CompactPCI

Abstract: A peripheral data storage subsystem is for use with a computer system. The computer system has a host PCI bus and a serial PCI host bus adapter coupled to the host PCI bus. The peripheral data storage subsystem includes a plurality of data storage devices and a data storage device to parallel PCI interface that is coupled to each of the data storage devices, a parallel PCI to serial PCI interface coupled to the data storage device to parallel PCI interface and a serial PCI link interconnect. The serial PCI link interconnect couples the parallel PCI to serial PCI interface of the peripheral data storage subsystem to the serial PCI host bus adapter of the computer system.

Abstract: A method and system for translating peer-to-peer access across multiple Peripheral Component Interconnect (PCI) host bridges within a data-processing system are disclosed. In accordance with the method and system of the present invention, a processor and a system memory are connected to a system bus. A first and at least a second PCI local buses are also connected to the system bus via a first PCI host bridge and a second PCI host bridge, respectively. The two PCI local buses have bus transaction protocols that are different from those of the system bus. At least one PCI device is connected to each of the two PCI local buses, and shares data with the processor and the system memory. In addition, each PCI device shares data with the other PCI device as peer-to-peer devices across multiple PCI host bridges. A sequence of transactions is controlled through the two PCI host bridges to prevent a deadlock condition by not allowing a subsequent peer-to-peer write request destined for one of the two PCI local buses to be blocked from making progress through the two PCI host bridges.

Abstract: A CompactPCI-based computer system including a chassis and a mid-plane board. The mid-plane board forms bus circuitry, and is positioned between a front and back of the chassis. The chassis and the mid-plane board combine to define a plurality of CompactPCI form factor slots, including front slots and back slots. At least one of the front slots and at least one of the back slots are system slots configured to receive and provide independent bus connections for respective CompactPCI form factor system processor cards. In one preferred embodiment, the mid-plane board is configured to provide a bussed connector at a first front slot and at a second back slot, and a transition connection at a first back slot and a second front slot. With this one preferred embodiment, a one- or two-unit wide system processor card can be loaded into the first front slot, and another one- or two-unit wide system processor card can be loaded into the second back slot.