Abstract: Spare chips are employed together with a replacement algorithm to replace chips in memory array when failure is generally more extensive then unrelated cell fails in the memory chips. That is, substitution will be made if an error condition is a result of the failure of a whole chip (chip-kill), a segment of a chip (island-kill), a column of bits of a chip or a row of bits of a chip but will not be performed when it is due to a single failed cell. The replacement of a chip with a chip-kill or with an island-kill is done on the fly and involves only a row of the memory chips or elements leaving other elements of the memory unaffected by the replacement.

Abstract: A block associative memory includes a plurality of memory cell arrays (70 and 72) arranged in rows and columns. Addressing of memory cells in the arrays (70 and 72) loads the data contained in one row thereof into a row of sense amplifiers (74). The selected row constitutes a block of memory. The data in the accessed block is compared with key data from a key data generator (20) in an equalizer circuit (90). The data in a given row or block is arranged in word groups. Each word group is compared with the key data and a match output generated for each data word group matching the key data word group. This match is decoded to output the column location of that word. The steps of retrieving the block from memory and associating the block with the key search data is performed in a single step and then additional blocks are selected for association with the key data word.

Abstract: The data elements for a column of a table are fetched from irregular address locations in memory and stored as vector data with a regular address increment. Vector designating data is also generated which includes at least the first element address of the stored vector data and the increment of the vector. The vector data is processed by a program routine which can perform the processing required by a selected command and which includes vector instructions each designating at least one set of vector data elements to be executed, in such a manner that vector data elements are fetched successively from the data storage device and are supplied successively to a pipelined arithmetic or logical operation unit.

Abstract: A task control structure for transferring tasks from a storage device to a system memory and for controlling execution of tasks, and a document manager for loading document information in the form of document data structures from the storage device to the system memory and managing access to the data structures by the tasks are using task control blocks to manage the execution of tasks and document control blocks to manage access to the document data structures by the tasks. Each document file has a document control block and the document files and the document control blocks are designed to represent and relate to the structure of documents. Each document file has at least one page including at least one area, each containing at least one type of information. Each area including, in an area containing text information, at least one column for containing text information including at least one line, each line including a string of at least one text character, a reference to attribute applying to the characters or the string, and references to external data items associated with the line. A screen manager is used for creating visual display screens, each screen having a virtual screen with one or more viewpoints onto data to be displayed. The screen manager includes a control structure containing information relating each screen to a corresponding task, and, for each screen, information describing certain properties of the screen, and information relating the screen to the data residing in the document structure to be displayed.

Abstract: Dual interrelated distillation columns are disclosed wherein the heat for a first column is transferred by thermal conduction through a common wall or surface to a second column to increase efficiency and decrease waste of energy. In one embodiment, the first heat generating column is a cylindrical column, and the second column is an annular column concentric to the first column. This concentric arrangement permits the heat generated in the first column to flow outwardly into the second column, thereby improving its efficiency and reducing the heat loss. Typically, the inner first column is a high pressure rectifying column, and the outer concentric column is a stripping column. In an alternate embodiment, the inner column can simply be a portion of a high pressure distillation process, and the outer column is a portion of a lower pressure distillation column. In alternate embodiments, the rectifying apparatus can assume a variety of shapes such as a plurality of packed tubes which extend through the stripping column or a corrugated configuration or rectangular configuration as desired.

Abstract: A redundant memory circuit (18) having a memory for storing information in a matrix of interconnected rows and columns, and a row (42) and a column (80) address decoder to access the rows and columns. The memory has a redundant row or rows to replace a defective row or rows in the matrix and a programmable decoder (56) which is programmed with the row address of the defective row to access the redundant row. The row (42) and column (80) address decoders are used to access the defective row and to sequentially access the columns so as to entirely disconnect the defective row from the columns. The programmable decoder (56) is then programmed with the defective row address, bit by bit, in response to the column addresses, to access the redundant row. After this procedure, a verification circuit (70) can be used to verify that the redundant row can be accessed and that the programmable decoder (56) is properly programmed to decode only one address to one row.

Abstract: A static random access memory arrangement provides for accessing a desired number of bits (i.e., a byte) simultaneously by placing the accessed columns adjacent one another. For example, if the memory provides 8 bits when accessed, then a group of 8 adjacent columns is addressed, whereas the prior art provided for accessing one column out of each of 8 separate groups. The present scheme provides for improved utilization of spare columns for redundancy purposes, and also allows for partial row selection for reduced power consumption and noise.

Abstract: A system and method for manipulating a plurality of data records. Each record is comprised of a plurality of bits and is identified by a unique record address value. A portion of each record comprises a keyfield consisting of one or more sub-keyfields, each having a different order of significance. The sub-keyfield value of greatest significance of each record is utilized to enter the unique record addresses into a column of a compressed matrix memory means in a logical row corresponding to the sub-keyfield value of that record. The column entries of the set compressed matrix memory locations are then arranged in order of row position, and the column entries derived from the same row are grouped together. The process is successively repeated, separately for each group of duplicate column entries, for the sub-keyfield value of next greatest significance of each record in the group as long as at least one group of duplicate column entries remain and all sub-keyfields have not been processed.

Abstract: The columns of a memory array are accessed by a plurality of column decoders, each decoder selectively accessing one column in a respective group of columns. Each column decoder can be connected to a respective data line by way of a first transistor, and the data line can also be connected to the decoder of a preceding group of columns by way of a second transistor. The second transistor associated with the first stage can connect the first data line to a spare column decoder accessing a spare group of columns. The conditon of each pair of first and second transistors is controlled by way of a respective normally closed fuse, and generally each column decoder is connected by its first transistor only to its respective data line. However, if defects are found in a group of columns, the associated fuse is blown to isolate that group from its data line. The second transistor is then rendered conductive to connect the data line to the preceding column decoder. Similarly, the data line of each preceding group is connected to the preceding column decoder with the first data line being connected to the spare column decoder.

Abstract: A semiconductor integrated circuit, such as a high-density, dynamic read/write memory containing an array of rows and columns of memory cells, is constructed to allow high speed testing to identify row line faults in one example, and to identify column or sense amplifier faults in another example. Row lines for the array in a dynamic RAM may contain detector circuits activated in a special test mode to produce a data output indicating integrity of each row line without requiring the access of the cells in the array in complex data patterns. The connection between bit lines in the array and sense amplifiers may be shifted or transposed in another embodiment to distinguish between column or sense amplifier faults; this construction also allows rapid loading of test patterns.

Abstract: An educational baby toy in which a number of lamps of different colors are mounted on the upper surface of the housing in transverse rows and columns. Manually actuable buttons are likewise mounted on the upper surface with one button mounted adjacent each lamp for causing, when actuated, illumination of that lamp, one button mounted adjacent each row, column and diagonal thereof for causing, when actuated, sequential illumination of each lamp of that row, column or diagonal and three buttons for causing, when actuated, illumination of each of said lamps in two different given sequences and in a random sequence.

Abstract: A programmable read-only memory device of a junction destruction type is provided with a test circuit for the purpose of detecting a parasitic thyristor effect which may occur in the data programming operation by the user. The test circuit includes first and second additional row lines, a first diode connected between the first additional row line and one column line, a second diode connected between the second additional row line and another column line adjacent to the one column line, and a transistor of a base-open type connected between the second additional row line and the one column line.

Abstract: A semiconductor integrated circuit, such as a high-density, dynamic read/write memory containing an array of rows and columns of memory cells, is constructed to allow high speed testing to identify row line faults in one example, and to identify column or sense amplifier faults in another example. Row lines for the array in a dynamic RAM may contain detector circuits activated in a special test mode to produce a data output indicating integrity of each row line without requiring the access of the cells in the array in complex data patterns. The connection between bit lines in the array and sense amplifiers may be shifted or transposed in another embodiment to distinguish between column or sense amplifier faults; this construction also allows rapid loading of test patterns.

Abstract: Current North American specifications provide design criteria to prevent local failure of H-shaped columns when flanges or moment connection plates are welded to the column flange. This design criterion was developed strictly for these types of connections. Application of these criteria when bolted end-plate connections are used for welded and welded-bolted connections. Unnecessary use of column stiffeners may result in opposite beam flanges being tensioned. Installation of column stiffeners is expensive and stiffeners can interfere with weak axis framing into the column. If stiffeners between the flanges of H-shaped columns can be eliminated, the fabrication process is greatly simplified.

Abstract: Our objective in using column switching is primarily to achieve the desired separation in the minimum analysis time. Complimentary to this aim is the need for sample and column cleanup followed by column re-equilibration. Finally, all operations should be capable of automation. Fundamental to column switching methodology is the concept of Zone cutting, where part of the chromatogram is transferred to another column. This forms the basis of sample cleanup and is a very versatile and powerful method. Multiple zone cutting is also possible to further increase the scope of cleanup or to minimise analysis time. Zone cutting is also complimentary to the techniques of trace enrichment and recycling. Examples will be given involving the use of these techniques in the analysis of complex matrices such as urine, plant extracts, wine and serum. The latter will be used to propose a novel approach to the quantitative analysis of anti-convulsants in serum using hexobarbital as internal standard.

Abstract: A dynamic read/write memory array has a column decode and data input/output arrangement constructed to compensate for large capacitive loads in the I/O circuitry. In a first stage, a buffer is employed between sense amplifiers and segmented intermediate I/O lines. Each segment is a small fraction of the I/O load. First-level column decoding selects one column for each segment. A second level of column decoding employs tri-state buffers which can only be activated during a read with the proper column address. When writing, all buffers are in the high impedance state for reading while the selected buffer is written into through decoded pass gates.

Abstract: The invention relates to a camera carriage having a vertical lifting column, serving for the height adjustment of the camera, consisting of an outer column part resting on the underframe, a middle column part which can be telescopically extended out of the outer column part and a central column part which can in turn be extended out of the middle column part and which carries the camera. In order to permit a frequent extending of the lifting column, according to the invention the drive device comprises a reversible electric motor, connected to the outer column part, for the drive of at least one endless chain, which is guided between the middle and the outer column part by means of two deflecting wheels parallel to the column axis and at one of the runs of which the middle column part is secured. Furthermore, in the central column part there is tensioned at least one endless traction cable which extends parallel to the axis and which, guided via a pair of deflecting rollers on at least one roller carrier extending into the interior of the column and connected to the middle column part, is connected by one of its runs to the central column part and by its other run to the upper free end of a clamping rod which is secured to the outer column part and likewise extends into the central column part.

Abstract: An integrated dynamic write-read memory includes at least one redundant row and/or column initially excluded from normal operation of the memory but available for normal operation as a replacement. At least one row decoder is connected to the memory matrix and at least one column decoder is connected to the memory matrix for addressing. A column address pulse is fed to the memory matrix for initiating addressing by matrix columns and a row address pulse is fed to the memory matrix for initiating addressing by matrix rows. A normal data path leading out of the memory matrix includes a tristate output connected to the normal data path and actuated by addressing with the stored digital data. Another decoder is connected in the normal data path between the memory matrix and the tristate output with an output connected to the tristate output. The other decoder blocks the normal data path from the memory matrix to the tristate output upon addressing each row or column of the portion of the memory matrix intended for normal operation replaced by a redundant row or column and upon simultaneous external activation of the other decoder. The other decoder also indicates the insertion of a redundant row or column in place of a row or column in the portion of the memory matrix intended for normal operation with the appearance of a uniform indicating signal at the data output.

Abstract: PURPOSE:To perform high-speed access, by starting a page mode cycle and accessing a memory if a new column address is the same as before when column addresses are monitored. CONSTITUTION:When a new column address supplied during access to the memory is the same as the output of a latch as the last column address, a comparator 3 generates a coincidence signal, which allows the mode transition of a controller 5 to a page mode, and an address is determined only by specifying a new row address of a memory element. Thus, the access is speeded up.

Abstract: In a dynamic type MOSRAM of the address multiplexing system wherein column selecting address signals and row selecting address signals are time-serially multiplexed and applied to the memory, an individual row address buffer R-ADB and column address buffer C-ADB are provided. Their outputs are multiplexed by a multiplexor MPX on common address lines CR-ADLs, in order to reduce the area occupied by those lines. Thus, the column address buffer can be brought into a precharged status without awaiting the end of the operation of the row address buffer. Accordingly, in the case where the row address buffer and the column address buffer are to be continuously operated at an enhanced speed, the enhancement of the operating speed is not limited by a period of time taken for precharging the column address buffer. Accordingly, the operating speed of this RAM can be enhanced.

Abstract: PURPOSE:To improve the secret degree of a file, by controlling the access to the file through a card user of a console unit by ranking the access. CONSTITUTION:After inputting a secret code H1 by depressing a key K on a keyboard 2, a card 4 is inserted into a reading part 3. While referring a table 7, a matching part 6 compares the secret code H1 with a read-out identification code I1 and identifies that the user of a card Y is rank A to send the code A to a discriminating part 10. The discriminating part 10 checks the rank column e2 of a table 11 and reads out respective data in R (read), W (write) and f1-f3 (files) corresponding to the code A to discriminate these data. Since data 1 are written in all the columns, access to the files F1-F3 are permitted and reading and writing also are permitted. In case of rank D, access to the files is inhibited.

Abstract: In this column, I will discuss the principles involved in getting strategic plans implemented and what the professional planner's role should be vis‐a‐vis these principles. I will also give examples of how these principles are applied in practice. My comments will apply especially to decentralized multibusiness companies; but the principles should be generally applicable.

Abstract: PURPOSE:To reduce the capacity of a transaction table by making it possible to change easily a transaction unit price in accordance with transaction in the transaction processing where the transaction table storing a goods code, a goods name and a unit price data is used. CONSTITUTION:The goods code A, the goods name (a), and the unit price data Ia are stored in the columns (e), (f), and (g) of a goods table P respectively. When a classification key K on a keyboard 2 is operated to input designating data (p), a retrieving part 4 accesses the transaction table P to take out the goods code A, and this code is displayed out on a display part 6. If the operator wants to change the unit price of this goods, the unit price data, for example, 0.8Ia and quantity data Da from the keyboard 2 are inputted in order, a processing part 7 attains the product of them, and the attained data is stored in the column h2 of a data area 12 of a file 8.

Abstract: PURPOSE:To improve both cache hit factor and tag memory use efficiency, by providing a tag memory control circuit which informs the level information to a clearing circuit in order to dissolve a significant display flag which causes the invalidity. CONSTITUTION:A tag memory control circuit 8 performs an update of a tag memory 2 owing to loading during a mishit as well as the control of invalidity of the memory 2 to an invalidity request K given from another data processor. Either one of levels of an invalidated stack circuit 5 contains a significant display flag P with no access request H nor invalidity request K. In such a case, the control of invalidity is carried out. An access is given to the level of the circuit 5 from a certain level of the flag P in accordance with a prescribed procedure. Then a validated address C and an invalidated column R are delivered to the memory 2 to designate the position to be invalidated, and ''0'' is written to a V bit S at the designated position of invalidation. At the same time, the dissolved level information T is delivered to a clearing circuit 6 for the invalidated level of the circuit 5.

Abstract: A game of chance wherein there are several rows of spaces, say three, arranged in columns and containing symbols placed at random. All of the spaces are masked to render the symbols invisible. A symbol for the various columns is called out periodically and a player attempts to guess that space in which the symbol called out is located. A successful attempt is called a match. There is an array of further spaces, one for each row and, as the last column is uncovered there is called out a desired relative performance of matches, e.g. "most" or "least," and the player seeks to select that row in which the desired relative performance occurs, based on symbols already uncovered.