Abstract: A dot matrix converter comprising means for providing an original character pattern comprising a dot matrix; means for dividing the original matrix into row groups and column groups, the number of groups being respectively one greater than the row difference and the column difference between the original matrix size and a desired matrix size to which the original matrix is to be converted; row (or column) size converting means which compare the individual opposed bits in the rows (or columns) on the opposite sides of dividing lines between adjacent row (or column) groups and inserts a logical "1" bit between the compared bits when both bits are logical "1" or inserts a logical "0" bit in all other cases, thereby effecting the addition of one row (or column) between the divided adjacent row (or column) groups; and column (or row) size converting means which compare the individual opposed bits in the columns (or rows) on the opposite sides of the dividing lines between adjacent column (or row) groups, and inserts a logical "1" bit between the compared bits when both bits are logical "1" or inserts a logical " 0" bit in all other cases, thereby effecting the addition of one column (or row) between the divided adjacent column (or row) groups.

Abstract: A relational data base is herein defined as a collection of normalized relations (relations in first normal form) and a collection of domains. A normalized relation may be viewed as a table, wherein each row of the table corresponds to a tuple of the relation, and the entries in a given column belong to the set of values constituting the domain underlying that column. The domains of a data base have an abstract existence apart from the data base relations.The data base also includes various types of semantic integrity rules, which specify additional properties of the data in the data base. One such type of semantic integrity rule is the domain definition. A domain definition includes the precise description of the set of values (objects) constituting the domain. In a normalized data base, all domains are sets of atomic data values. A domain definition also includes a specification of the ordering on the values in a domain, for comparability purposes. In addition, a domain definition contains a specification of the action that is to occur if an attempt is made to violate the restriction that every entry in each column of a relation must be from the underlying domain of that column.A nonprocedural language permitting the high level expression of domain definitions is defined. Language details and examples are presented, and the syntax and informal semantics of the domain definition language are given. This approach to domain definition is analyzed in terms of its impact on other aspects of data base semantic integrity. The relationship with the data base system in general is outlined. An analysis of intradomain and interdomain comparability is included. An introduction to relevant implementation issues is also presented. Emphasis is placed on a general approach to implementation and implementation techniques, rather than on a specific system.

Abstract: A relational data base system utilizing magnetic bubble domain storage. The bubble domain storage is located on a magnetic chip and includes storage circuitry for storing bubble domains in columns and rows. The bubble domains are coded to represent data, and the rows and columns of bubbles correspond to tables of data which are determined by various relations. Current activated transfer gates located on the magnetic chip are used to select a particular row or a particular column of bubble domains for accessing. The magnetic chip also includes a write circuit for writing bubble domains into storage and a read circuit for reading bubble domains removed from storage. Located off the magnetic chip are column addressing circuits, row addressing circuits, interface circuitry, and a computer central processing unit. The interface circuitry is located between the central processing unit and the bubble domain storage chip, while the column and row addressing circuits provide inputs to a transfer control circuit that is used to activate selected current carrying lines when it is determined to access a particular row or column of bubbles in storage. New information can be entered into any of the stored tables of bubble domains, and information can be removed from any of the stored tables. Also, new tables of information can be provided in storage by combining selected rows or columns of tables already in storage.

Abstract: A data processing control apparatus comprises a main memory for storing a plurality of record data serially arranged with a record positioning code between the record data, each record data including a plurality of word data serially arranged with a word positioning code between the word data, the word data each including at least one character data; and a processing memory means having a row/column matrix which is address designated by the outputs of row and column counters for permitting each word data in the record data to be stored in its address. A specific row of a heading column in the matrix in the processing memory means is address designated to permit the address position data in this row to be sequentially shifted in a row direction. Specific codes, each written in an address position following a final character data, in the word data are counted by a counter while an address shift is effected in a column direction from an address position in the specific row. A word order memory is adapted to beforehand store a numerical value corresponding to the order of a word data to be selected from the record data and a coincidence circuit is adapted to detect a coincidence between the number of specific codes counted by the counter and a numerical value stored in the word order memory. When a coincidence output is generated from the coincidence circuit a data readout from the main memory to the processing memory means is inhibited by the coincidence output of the coincidence circuit and only a word data corresponding to a selected word order is delivered to the data processing memory.

Abstract: The "semantic integrity" of a data base is said to be violated when the data base ceases to represent a legitimate configuration of the application environment it is intended to model. In the context of the relational data model, it is possible to identify multiple levels of semantic integrity information: (1) the description of the domains of the data base, as abstract sets of atomic data values (domain definition), (2) the specification of the fundamental structure of the relations of the data base (relation structure specification), (3) the definition of the abstract operations which are meaningful in terms of the application environment (structured operations), and (4) the expression of additional semantic information not contained in the structure of the relations nor in the identities of their underlying domains (relation constraints). A high level, nonprocedural domain definition language facilitates the description of domains. Such a language allows the specification of the properties of the values constituting a domain, and the action that is to occur if an attempt is made to update a column entry such that it does not belong to the underlying domain of that column. The specification of relation structure and structured operations can also be accomplished by means of high level integrity (sub)languages. A relation constraint has three components: (1) the assertion predicate on the state of the data base or on transitions between data base states), (2) the validity requirement (the occasion(s) at which the assertion must hold), and (3) the violation -action (the action that is to occur if the assertion does not hold at a time when it should). Relation constraint specification can be related to an expression framework (classification scheme) which is useful for the construction of a relation constraint language and specification methodology. Assertions are more than expressions of some relationships among different values in a data base; an assertion singles out the data that is constrained, the states the properties that this data must possess. A classification is provided of the various predicate types used to identify constrained data and to state the properties that they are to possess. A semantic integrity subsystem (of a generalized relational data base management system) can support the generation and maintenance of integrity specifications, verify that these specifications are met by the data base, and take appropriate action if violations are detected.

Abstract: A low table about the height of a coffee table, to be retailed as a kit of parts which can be quickly and simply assembled without tools, and which is made essentially of heavy cardboard or fiberboard finished to resemble wood, and consisting of a flat base, a hollow column fixed to said base, and a table top fixed to said column. The column is weighted with sand which is immobilized at the bottom of the column by means of hot wax or a similar agent.

Abstract: A matrix switch comprises a lamination of several layers in which first and second piezoelectric films have row and column electrodes, respectively, arranged in parallel on their first surfaces. A ground electrode is between said row and column electrodes. The operating electrodes are at cross points which are deformable to result in two piezoelectric output signals from each cross point; one between ground and an operating row electrode, and the other between ground and an operating column electrode.

Abstract: A new system, that of matrix grammars, for two-dimensional pattern processing, is introduced. A hierarchy, induced on Chomsky's is found. Language operations such as union, catenation (row and column), Kleene's closure (row and column), and homomorphisms are investigated. It is found that the smallest class of these languages may serve as the class of regular arrays, which is defined as the smallest class of arrays closed under union, catenation (row and column) and Kleene's closure (row and column). Eight possible ways of defining a matrix language are discussed and it is suggested that one of them may lead to a normal form for matrix grammars. The method is advantageous over others on several points. Perhaps the most interesting of all is that it provides a compromise between sequential methods which take too much time for large arrays and parallel methods which usually take too much hardware for large arrays.

Abstract: An apparatus and method for reading punched cards having data columns parallel to one edge of the card with each data column containing a coded pattern of punches wherein the card is moved past an aligned array of sensors that are mounted to be in alignment with each data column of the passing card. The invention provides for synchronously supplying a parallel digital signal that accurately represents the characters encoded in each data column even though the aligned sensor array is not maintained in precise alignment with the passing data columns and/or the card is not moved past the array at a uniform rate. The synchronous reading is accomplished by sequentially performing two detection sequences to detect two conditions that occur as the card and encoded data columns move by the sensors. The first detection sequence constitutes a determination that at least one unpunched card region has passed by each sensor since the start of the first detection sequence. In effect, the first detection sequence detects the passage of an unpunched region separating adjacent data columns even though the moving data column and sensor array are misaligned with one another to the extent that various sensors are exposed to a punched data location at each moment of time. The second detection sequence is automatically initiated following the first detection sequence and constitutes a determination that one data punch has completely passed by a sensor to effectively determine that an encoded data column is just then moving beyond the sensor array. The sensor signals immediately prior to the detection of this condition constitute, and are supplied as, a digital signal representing the character encoded in the passing data column. Since the first and second detection sequences are sequentially performed in accordance with the pattern of punches in the encoded data columns, synchronous card reading is effected to read each character encoded on the card.

Abstract: Provided is a semiconductor memory device comprising a pair of data input lines, a pair of data output lines, memory cells arranged in the form of a matrix, the memory cell of each column being connected between a pair of data lines, the memory cell of each row being connected to a row selection line, a memory cell selection circuit for generating column and row designation signals in order to select a desired one of said memory cells, a switching circuit disposed in each column and turned on upon receipt of a column designation signal from the memory cell selection circuit to connect the data line to a corresponding one of the data input lines, and a data detection circuit connected between the pair of data lines of each column and adapted, upon receipt of a column signal from the memory cell selection circuit, to transmit an inverted signal of a signal on the data line onto the data output line.

Abstract: SUMMARY A geometric characterization of connectedness in a two-way design is given This characterization is used to study four different analyses of the usual hypotheses about row effects, column effects and interactions in two-way designs with empty cells

Abstract: A relay matrix which constitutes an array of switches providing connection points between a set of "horizontal" inputs and a set of "vertical" outputs, has n relays per column disposed in p columns. Each relay column is associated with a register which fulfills the functions of controlling and storing the state of the relays of the column. The invention can be applied to switching systems and in particular to automatic telecommunication exchanges.

Abstract: GPMX is an extension of GPM, a simple, elegant yet powerful language independent macro processor described by Strachey. Unextended, GPM is not suited for preprocessing languages which use column position and end of record to delimit statements. Examples are FORTRAN and many assembly languages. Many programmers are constrained to work in such limited languages and GPMX is a simple yet powerful tool for extending and modifying these languages. Others have developed preprocessors dedicated to a particular language. This has advantages for the implementor, but requires the user to learn a different preprocessor for each language he uses. GPMX is designed to work on any language so that the (non-trivial) effort of learning to use it need not be repeated later. Extensions in GPMX include macro control over: files, record input and output, spacing, conditional macro processing and compilation, access to input and output buffers, and dynamic changing of the macro flag characters. Most of the extensions are accomplished simply by putting the control information on the macro stack where the processor has access to it (ala von Neumann). GPMX has been implemented in ANS FORTRAN for portability. Several applications are shown, including GO-TO free control structures for FORTRAN. Source is available.

Abstract: Following the general lines set forth in [1] for the introduction of probabilistic concepts into the practical design of imperfection-sensitive structures, numerical results are presented pertaining to the probability of failure, under random axial load, of an elasto-plastic column studied earlier under given load [2]. Several possible approximate procedures to reduce the needed amount of calculations are proposed and discussed.

Abstract: A semiconductor memory has a matrix in a chip. The matrix consists of r rows and s columns, with r.s. semiconductor storage locations with two defined, different electric states. Storage locations belonging to one row or one column can be individually addressed through wires allocated to the corresponding matrix row or column, and through a first decoder selecting the row wires, and a second decoder selecting column wires. The two decoders are connected in series w.r.t. the voltage source supplying them. The decoder realising the selection according to the matrix rows and the decoder realising the selection according to the matrix columns are sequentially switched w.r.t. the voltage supply. Power loss is thereby reduced by half, while the switching delay remains the same.

Abstract: PURPOSE:Improvement in the efficiency of a buffer memory by one to one code conversion of a column address in a random manner to evenly distribute the column address thereby ensuring equalized use for the buffer memory

Abstract: PURPOSE:A display equipment is placed on a display column of keyseat which is on a board of coordinate analysis equipment by the matter of which a coordinate data of display column is put in a controlling device, it obtains command out-put corresponding to a display column of keyseat, then various equipments are controlled.

Abstract: : An efficient and numerically stable method is presented for the problem of updating an orthogonal decomposition of a matrix of coulmn (or row) vectors. The fundamental idea is to add a column (or row) analogous to adding an additional row of data in a linear least squares problem: A column (or row) is dropped by a formal scaling with the imaginary unit followed by least squares addition of the column (or row). The elimination process for the procedure is successive application of the Givens transformation in modified (more efficient) form. Some suggested computational tests for determining signs of various controlling parameters in the revised simplex algorithm are also given. (Author)

Abstract: Row wires are connected to a supply voltage through row switches cyclically operated by a switching device. Column switches for column wires are closed during operationg period of a row switch in accordance with signals to be applied to the loads. Signals determining the switching state of the loads (1) are stored in storage location of a writing/reading store (15), arranged in a matrix. Signals corresponding to a switching matrix row (3) are cyclically read out by means of address signals, and applied to a control circuit (23) selecting signal voltages for loads (1) in this row. This control circuit (23) also controls the operation of column switches.

Abstract: A systematic procedure to locate a faulty cell in a column (row) of the main array (rotated array) in cutpoint cellular arrays is presented. It is assumed that a cell failure may be due to stuck-at faults at the input/output leads of the cell or due to stuck-at faults within the cell.

Abstract: The store consists of a number of matrices of npn transistors arranged in rows and columns, with a transistor at each "data point" in a matrix. A particular data point, or transistor is assessed by driving a current down the appropirate row and column conductors, the row conductors being attached to the emitters of a row of transistors, whilst the column conductors are attached to the bases of a column of transistors. The collector of each transistor is connected via a resistance to a suitable current and voltage supply. To write a "one" into a particular location the appropriate row and column are chosen and a current is driven through the collector resistance sufficient to melt and open circuit it.