Topic
Coded mark inversion
About: Coded mark inversion is a research topic. Over the lifetime, 35 publications have been published within this topic receiving 110 citations.
Papers
Patent•
NEC1
TL;DR: In this article, a phase-locked regenerative circuit with a low-pass filter, a voltage-controlled oscillator, and a phase comparator is presented, where the output of the oscillator is sampled by a flip-flop for sending an output signal to the VCO through the lowpass filter.
Abstract: In a digital transmission system, a clock regeneration circuit includes a phase-locked loop having a low-pass filter, a voltage-controlled oscillator connected thereto, and a phase comparator for supplying to the low-pass filter a signal representative of the phase difference between an incoming two-level data bit stream and the output of the voltage-controlled oscillator. The incoming data bit stream is converted into a plurality of parallel data bit streams and fed to a multi-level quadrature amplitude modulator in response to a clock signal derived from the output of the voltage-controlled oscillator and converted into an outgoing multi-level digital signal. An incoming CMI (coded mark inversion) coded binary signal is sampled by a flip-flop for in response to the output of the voltage-controlled oscillator to supply an output signal to the VCO through the low-pass filter.
25 citations
TL;DR: An intensity modulation/frequency-shift keying (IM/FSK) orthogonal modulation scheme is achieved by direct modulation of a distributed feedback laser source using its adiabatic chirp characteristics, showing the viability of this scheme for distances up to 25 km.
Abstract: In this work, an intensity modulation/frequency-shift keying (IM/FSK) orthogonal modulation scheme is achieved by direct modulation of a distributed feedback laser source using its adiabatic chirp characteristics. Optical frequencies for "1" and "0" bits are separated only 0.7 GHz, obtaining a narrow-FSK modulation and, accordingly, a low residual intensity modulation. Ethernet frames at 1.25 Gb/s (GbE) are transmitted with a label inserted using coded mark inversion codification at a 155-Mb/s rate. Error rates for the Ethernet payload and for the label have been measured for different payload extinction ratios, showing the viability of this scheme for distances up to 25 km
11 citations
TL;DR: The design and performance features of a successfully developed optical intraoffice transmission system operating at 100-400 Mbits/s, which makes use of coded mark inversion (CMI) coding to ensure bit sequence independence (BSI) and good error-monitoring capability is presented.
Abstract: This paper presents the design and performance features of a successfully developed optical intraoffice transmission system operating at 100-400 Mbits/s. The keys to the commercial realization of this simple, highly reliable, and low-cost system are the employment of the 1.3 μm LED and graded-index multimode fiber. Additionally important, the system makes use of coded mark inversion (CMI) coding to ensure bit sequence independence (BSI) and good error-monitoring capability. Experimental results have clarified the optimum bandwidth of the low-pass filter at the receiver end and the commercially attainable transmission distance. Furthermore, an available system gain of 15.4 dB is demonstrated through 400 Mbit/s transmission experiments. This value enables transmission over distances in excess of 4 km through multimode fiber (900 MHz \cdotp km, 0.8 dB/km).
9 citations
Patent•
NEC1
TL;DR: In this article, a clock regeneration circuit for extracting timing information from a CMI (Coded Mark Inversion) coded signal is presented, where the output of a voltage controlled oscillator is sampled by a flip-flop at timings corresponding to the boundaries of the time slots of a coded signal.
Abstract: A clock regeneration circuit for extracting timing information from a CMI (Coded Mark Inversion) coded signal. The output (204) of a voltage controlled oscillator (4) capable of oscillating at the clock frequency of the CMI coded signal is sampled by a flip-flop (2) at timings corresponding to the boundaries of the time slots of a CMI coded signal (201). A low pass filter (3) is connected to the output (202) of the flip-flop 2. The phase of the output (204) of the voltage controlled oscillator (4) is controlleJ by the output (203) of the low pass filter.
8 citations
Patent•
18 Apr 1989TL;DR: In this article, a CMI block synchronization circuit includes a clock deriving circuit, CMI decoding circuit, signal selection determining circuit, and a selection circuit, where one of the count values is equal to or higher than a setting value and another count value is lower than another setting value is regarded that a block asynchronization is caused in decoding the CMI code signal.
Abstract: A CMI block synchronization circuit includes a clock deriving circuit, CMI decoding circuit, signal selection determining circuit and a selection circuit. In the clock deriving circuit, a clock CLKo having the same phase as a binary signal and a clock CLK.sub.π having a phase which is different 180° from the clock CLKo are derived from an inputted CMI code signal. In the CMI decoding circuit, the inputted CMI code signal is decoded by using the clocks derived and violating bits are detected. In the signal selection determining circuit, the clocks CLKo and CLK.sub.π are counted respectively. Only when one of the count values is equal to or higher than a setting value and another count value is lower than another setting value is it regarded that a block asynchronization is caused in decoding the CMI code signal. In this case, the decoded output being selected until that time is changed over to another decoded output, whereby the block synchronization is retained even during burst errors.
7 citations
Related Topics (5)
Performance Metrics
| Year | Papers |
|---|---|
| 2014 | 1 |
| 2013 | 1 |
| 2010 | 1 |
| 2009 | 2 |
| 2006 | 1 |
| 1998 | 1 |